An IP2 Improvement Technique for Zero-IF Down-Converters

Darabi, Hooman; Kim, Hea Joung; Chiu, J.; Ibrahim, B.; Serrano, L.

doi:10.1109/isscc.2006.1696243

Cited by 23 publications

(9 citation statements)

References 4 publications

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“…The concept of IIP2 calibration is to sense and correct the dc offset with an analog or digital feedback loop [33]- [36]. Some correction approaches for mixers include adjusting the LO bias [33], the load resistor/capacitor banks [34], the current source load [35], or injecting current at the mixer output [36].…”

Section: Discussionmentioning

confidence: 99%

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Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Zhang

Sánchez-Sinencio

2011

IEEE Trans. Circuits Syst. I

299

144

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This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization issues for emerging reconfigurable multiband/multistandard and wideband transceivers. Furthermore, we highlight the impact of CMOS technology scaling on linearity and outline how to design a linear LNA in a deep submicrometer process. Finally, general design guidelines for high-linearity LNAs are provided.

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Section: Discussionmentioning

confidence: 99%

“…As oxide thickness decreases, poly-gate depletion increases, and the nonlinear gate capacitance develops strong second-order derivatives with respect to , which contribute to significant third-order distortion in drain current, as shown in (36) and (37) [46] (36)…”

Section: Impact Of Technology Scaling On Linearitymentioning

confidence: 99%

Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Zhang

Sánchez-Sinencio

2011

IEEE Trans. Circuits Syst. I

299

144

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“…The design employs 0. 35 CMOS. The use of this technique is shown to improve IIP3 by 10 dB compared to a basic cascode.…”

Section: E Derivative Superpositionmentioning

confidence: 99%

“…In [35], for instance, a squarer is employed at baseband to generate an IM2 term which is subsequently subtracted from the output of the mixer, to cancel the net second-order term. An 18 dB average improvement in IIP2 is reported.…”

Section: A Active Current-commutating Mixersmentioning

confidence: 99%

Linearity Enhancement Techniques in Radio Receiver Front-Ends

Gharpurey

2012

IEEE Trans. Circuits Syst. I

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A key role in determining the overall performance of a communication link is played by the linearity of the analog sections of the transmitter and the receiver. Nonlinearity in the receiver can impact performance in several ways, including degradation in sensitivity, reduction in gain, and the appearance of spurious energy within the frequency band of interest from out-of-band sources. An overview of circuit and architectural techniques for enhancing receiver front-end linearity is presented. Two types of techniques are described, those that rely on device or circuit level linearization, through reduction of nonlinear coefficients, and those that rely on attenuation of undesirable interferers.

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“…Regardless of complex calibration techniques [4,5], in the extent of our knowledge, the solution presented for this problem in CMOS technology is using a LC filter for tuning C P capacitor in LO frequency [6]. In this way IIP2 improvement by Q dB can be achieved in which Q is the inductor quality factor.…”

Section: Introductionmentioning

confidence: 99%

A new technique for high IIP2 reconfigurable CMOS mixer in multi-standard receivers

Vahidfar

Shoaei

2007

IEICE Electron. Express

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Abstract:A new technique for addressing the challenging dynamic range required by CMOS multi-standard Zero-IF GSM and UMTS receivers is presented in this paper. This is achieved by LC tuning of the parasitic capacitors of mixer switching transistors in different frequency bands with an easily reconfigured new integrated variable inductor. Using this technique, a high IIP2 low noise mixer supporting DCS, PCS, UMTS and IEEE802.11 b-g standards is designed. The mixer achieves IIP2 higher than 70 dBm while the input refereed noise performance is 5 and 3.5 nv/sqrt(Hz) in DCS/PCS and UMTS respectively. The design is done in 65 nm CMOS technology.

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An IP2 Improvement Technique for Zero-IF Down-Converters

Cited by 23 publications

References 4 publications

Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial

Linearity Enhancement Techniques in Radio Receiver Front-Ends

A new technique for high IIP2 reconfigurable CMOS mixer in multi-standard receivers

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