An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

Abstract

A low specific on-resistance (R on; sp / SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features: a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on; sp . Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/ m from 48 V/ m of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and R on; sp . Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on; sp by 80% at the same BV.

The impact of heavy ion irradiation on the performance of novel REDI LDMOS power devices

“…Two important characteristic parameters of power MOS devices are the breakdown voltage and on-resistance. Tradeoff between BV and R on should be considered in the design of new structure power MOS devices [12][13][14][15][16][17]. A novel RES-URF dielectric inserted LDMOS (REDI LDMOS) is proposed and fabricated by adding a p + doping region and SiO 2 dielectric layer in the drift region, which leads to low electric field in the depletion region and high breakdown voltage as well as low on-resistance compared with the conventional LDMOS devices [18,19].…”

Improving breakdown voltage performance of SOI power device with folded drift region

“…For the conventional silicon-on-insulator (SOI) highvoltage device, high breakdown voltage (BV) needs a long drift region, which inevitably leads to a high specific onresistance and a serious manufacture cost of SOI integrated circuit. [1,2] An effective method of increasing BV is to introduce an oxide trench in the drift region, [3][4][5] and the trench technology has been widely used in the design of the devices. [6,7] The oxide trench in the drift region can decrease the high electric field near the gate and increase length of ionization integral, resulting in a high BV and mini cell pitch.…”