An LTE Uplink Receiver PHY benchmark and subframe-based power management

Själander, Magnus; McKee, Sally A.; Brauer, Peter; Engdal, David; Vajda, András

doi:10.1109/ispass.2012.6189203

Cited by 35 publications

(11 citation statements)

References 5 publications

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“…For example, [20] uses various types of instructions as attributes for multiple linear regression, [17] uses a regression-tree-based modeling, and [1] uses a nonlinear regression model. References [10] and [8] use various machine training approaches to predict software performance on multi-core processors. Reference [7] uses both static attributes such as numbers of different types of instructions and dynamic attributes such as number of cache misses for regression.…”

Section: Related Workmentioning

confidence: 99%

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Comparing DSP Software Performance Prediction Models at Source Code Level — From Analytical to Statistical

Hu¹,

Liu²,

Su³

et al. 2019

JSW

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Efficient performance prediction at source code level is essential in reducing the turnaround time of software development, particularly when the source code is subject to changes due to modification of problem specification. In this paper, we investigate and compare five performance prediction models from practical standpoint to determine the usefulness of these models. To verify the effectiveness of these models, we select a set of functions from PHY DSP Benchmark and TIC64 DSP processor for experiment. Comparing the predicted performance to the actual measured execution time, we observed that the relative prediction error generated from two of the five models are low and can thus be used for practical purposes.

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Section: Related Workmentioning

confidence: 99%

“…To this end, we have chosen eight most frequently used functions from the Long Term Evolution or LTE Uplink Receiver, a major part of the PHY benchmark [10] as the testing set of samples. PHY is an open-source benchmark developed by Chalmers University of Technology of Sweden and Ericson.…”

Section: Introductionmentioning

confidence: 99%

Comparing DSP Software Performance Prediction Models at Source Code Level — From Analytical to Statistical

Hu¹,

Liu²,

Su³

et al. 2019

JSW

View full text Add to dashboard Cite

show abstract

“…It contains three tasks: IFFT, deinterleaving, and demapping. A description of these processing tasks, as well as source code, can be found in [8].…”

Section: Wireless Receiver Signal Processingmentioning

confidence: 99%

Improving Latency in a Signal Processing System on the Epiphany Architecture

Brauer

Lundqvist

Mällo

2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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-In this paper we use the Adapteva Epiphany manycore chip to demonstrate how the throughput and the latency of a baseband signal processing chain, typically found in LTE or WiFi, can be optimized by a combination of task-and data parallelization, and data pipelining. The parallelization and data pipelining are facilitated by the shared memory architecture of the Epiphany, and the fact that a processor on one core can write directly into the memory of any other core on the chip.

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“…We assume proportional fair (PF) algorithm is used for LTE uplink [6]. With PF, the objective is to maximize MCS and layer to the processor load which expressed as workload for each subframe(described by percentage) in this paper is given in [7]. …”

Section: A Coordinated Multipoint Modelmentioning

confidence: 99%

“…We first model the CoMP uplink receiver, and give uplink SINR and capacity per user, then map them to MCS and spatial multiplexing layer, as well as how many PRBs should be allocated to each user. These parameters are closely related to power consumption of BS processing, we use the power consumption metrics from [7] to calculate total power consumption of uplink processing in BS.…”

Section: Introductionmentioning

confidence: 99%

Energy efficiency for coordinated multi-point uplink with dynamic voltage frequency scaling

Chen

Huang

2014

2014 IEEE/CIC International Conference on Communications in China (ICCC)

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We consider the uplink of coordinated multipoint (CoMP) communication system, which demonstrates a benefit of spectral efficiency, especially for cell-edge users. However, its energy efficiency remains to be evaluated. With the possible application of cloud computing into Base Station (BS), dynamic voltage frequency scaling (DVFS) of CPU based on workload is a good way to reduce power consumption of BS. Compared to non-coordinated architecture, the coordination obtains higher spectral efficiency at the cost of additional computation complexity, thus additional power consumption. DVFS techniques can adjust CPU very well to adapt workload variation. In this paper, We model signal to interference noise ratio (SINR) and spectral efficiency for CoMP, and map them to assignment of physical resource block (PRB), modulation coding scheme (MCS) and spatial multiplexing layer, which are related to processing capability requirement and power consumption, then we make use of DVFS to optimize power consumption. We run simulation to make a comparison of spectrum efficiency and energy efficiency between two BSs coordination and non-coordination, the average throughput increases about 50%, but the power consumption of BSs increases 200%, finally the ratio of power consumption to average throughput of CoMP increases about 100%.

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An LTE Uplink Receiver PHY benchmark and subframe-based power management

Cited by 35 publications

References 5 publications

Comparing DSP Software Performance Prediction Models at Source Code Level — From Analytical to Statistical

Comparing DSP Software Performance Prediction Models at Source Code Level — From Analytical to Statistical

Improving Latency in a Signal Processing System on the Epiphany Architecture

Energy efficiency for coordinated multi-point uplink with dynamic voltage frequency scaling

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