An NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall MOS transistor (NBiBMOS transistor)

Abstract

A concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar / sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (VcE or VDE) is less than the turn-on voltage of the n-p-n bipolar transistor (VBE = -0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and dc characterizing the NBiBMOS transistor structures which occupy -1.2 times the area of a single n-p-n bipolar transistor. The area occupied by the NBiB-MOS transistor which merges three transistors is the same as that of the previously described NBiMOS transistor which merges two transistors. In addition, the NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor because the body-source junction of the bypass NMOS transistor is forward biased.