A spread-spectrum clock generator (SSCG) with self-calibration circuit (SCC) is presented in this paper. By the use of self-calibration scheme, exploited the proposed linear circuit and a SCC, the gain of Kvco can be effectively reduced and the jitter performance is improved. Moreover, the proposed architecture provides an alternative technique for low Kvco instead of the commonly used methods for voltage-control oscillator (VCO) calibration. The SCC-based SSCG ensures phase locking under the process, voltage and temperature (PVT) variations. For spread-spectrum clocking, the digital MASH delta-sigma modulator and a 33-kHz triangular addressor is used. The proposed SSCG generates an output clock of 3 GHz and approximate 5000-ppm down spreading with a triangular-modulated shape. The SSCG has been designed in TSMC 0.18 μm CMOS technology. Operating at a 3-GHz clock rate, the peak-to-peak jitter of non spread-spectrum is 3.85 ps. The electromagnetic interference (EMI) reduction is larger than 20 dB with a triangular-modulated frequency of 3 2.985 GHz.
I. INTRODUCTIONAs the speed of computer operation increases, the highspeed system clock also accompanies large amounts of electromagnetic interference (EMI). In order to reduce the EMI, several methods are presented such as device shielding, EMI filter and spread-spectrum clocking (SSC) [1]- [5]. For example, the shielding to protect electronic device is the effective way to the EMI reduction. However, the method of shielding is not an economic way due to the area cost. Thus, a mechanism of SSC to adjust clock signal by frequency modulation is acknowledged as the effective and economic way. Accordingly, a spread-spectrum clock generator (SSCG) based on SSC can effectively spread out the power of the clock for the EMI issue.There are many methods to design a high-speed oscillator in phase-locked loop (PLL). The use of the LC tank voltagecontrolled oscillator (VCO) is popular, whereas the output frequency range is narrow. In addition, the narrow operating frequency range and large area cost leads to the difficulty for chip integration. A ring-based oscillator is the alternative architecture for clock oscillation. However, owing to process, voltage and temperature (PVT) variations, the large Kvco gain is designed to cover the required frequency. The high
