An on-chip frequency programmable test clock generation and application method for small delay defect detection

Pei, Songwei; Li, Huawei; Song, Junqiang; Liu, Jun; Li, Xiaowei

doi:10.1016/j.vlsi.2014.12.003

Cited by 6 publications

(1 citation statement)

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“…But, the FAST method also poses many challenges. The generation of the fasterthan-at-speed clock is addressed in [21]. The proper selection of test frequency and pattern by including the effects of IR drop is illustrated in [18].…”

Section: Introductionmentioning

confidence: 99%

Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects

Muthukrishnan,

Sathasivam

2023

IEEE Access

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Small delay defects (SDD) based test escapes are caused by the nature of transition delay fault (TDF) ATPG, which propagates the fault effect along the shorter path in the interest of run time. However, owing to the benefits of a lesser pattern count and complexity, TDF ATPG is the most feasible option for delay testing. Faster than at-speed testing enhances the likelihood of detecting SDD. To generate the optimal test option and prevent over or under-testing the circuit, it is necessary to select the appropriate test clock period. The recently introduced Weighted slack percentage (WeSPer) metric is used in this article to identify the best SDD test option. The method's benefit is combined with the proper selection of the optimal clock frequency to test the SDD. This article proposes an optimal test clock period selection method by considering the size of the smallest possible delay defect size that can fail the circuit during at-speed operation and the fault's propagation delay. The proposed method is applied to the set of ISCAS89 and ITC99 benchmark circuits to evaluate its effectiveness.INDEX TERMS Faster-than-at-speed testing, fault models, nanoscale devices, small delay defects, test quality metric, VLSI testing.

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Section: Introductionmentioning

confidence: 99%