An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications

Kumar, Abhash; Beeraka, Sai Manohar; Singh, Jawar; Gupta, Bharat

doi:10.1007/s00034-022-02237-7

Cited by 1 publication

(2 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, the accuracy can be expected high. The paper 10) proposed an on-chip training which is implemented by using SRAM. However, this approach may involve the addition of complex circuitry to handle backpropagation and weight updates, leading to a substantial increase in circuit size.…”

Section: On-chip Training (Conventional)mentioning

confidence: 99%

“…To improve the accuracy, several training schemes have been proposed. They include the on-chip training 10) and the in situ training [11][12][13] which seek to optimize models directly on the specialized hardware. However, despite the expectation, these methods have struggled with challenges such as the memory device limitations like endurance, 14) nonlinearity, and asymmetry 15) in switching.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A training method for deep neural network inference accelerators with high tolerance for their hardware imperfection

Gao,

Ohsawa

2024

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

We propose a novel training method named hardware-conscious software training (HCST) for deep neural network inference accelerators to recover the accuracy degradation due to their hardware imperfections. The proposed training method is totally conducted by software whose forward inference path and backpropagation reflect the hardware imperfections, overcoming the problems of the limited endurance, the nonlinearity and the asymmetry for the switching of the nonvolatile memories used in weights and biases. The HCST reformulates the mathematical expressions in the forward propagation and the gradient calculation with the backpropagation so that it replicates the hardware structure under the influence of variations in the chip fabrication process. The effectiveness of this approach is validated through the MNIST dataset experiments to manifest its capability to restore the accuracies. A circuit design is also disclosed for measuring the offset voltages and the open loop gains of the operational amplifiers used in the accelerator.

show abstract

Section: On-chip Training (Conventional)mentioning

confidence: 99%