An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements

Abstract

A scalable all-digital power supply noise analyzer with 20 GHz sampling bandwidth and 1 mV resolution is demonstrated in 32 nm CMOS technology for enabling low-cost low-power in-situ power supply noise measurements without dedicated clean supplies and clock sources. This subsampled averaging-based analyzer measures power supply noise in both the equivalent-time and frequency domains with low-resolution VCO-based ADCs. For equivalent-time measurements, the accurate impedance characterization of power delivery networks is simply done by measuring a clock-synchronized current-step response. For frequency-domain measurements, the digital random phase-noise accumulation technique is analyzed and verified to overcome the clock-and-noise correlation issue in autocorrelation measurements. In general large scale integrated circuits and systems, the entire power supply noise analyzer consumes negligible active and leakage powers because of the MHz-range sampling clock frequency and fully digital implementation with only hundreds of logic gates.

A High-Resolution Single-Photon Arrival-Time Measurement With Self-Antithetic Variance Reduction in Quantum Applications: Theoretical Analysis and Performance Estimation

“…If the DCO frequency has reached the limit due to circuit bandwidth or power limitations, then proportionally extending τ and T together can be an alternative way to achieve the fastest sampling option (TDCO,MIN  0.5•T), which can be simply accomplished by statically scaling the conversion gains of the analog circuits, i.e., KTAC, KVGA, and KDL, through the inherent calibration capability of the RSA measurement system [50]. Meanwhile, the nonlinearities and offsets due to analog-circuit nonidealities and mismatches can be pre-calibrated by RSA itself without any assistance from extra hardware [45], [49], [50].…”

“…The state-of-the-art TDC designs can satisfy some of these specifications, however, with trade-offs among the other performance metrics [1]- [4], [6]- [8], [16]- [44]. To simultaneously accommodate all performance requirements for the majority of quantum applications, a TCSPC system proposed in [45] incorporates the digital random samplingand-averaging (RSA) technique [46]- [49] into a two-step TDC procedure to enable high-resolution time-interval measurements without compromising the performance metrics among accuracy, dynamic range, linearity, and power/area efficiency. However, the slow conversion-rate of the RSA technique has greatly limited the broadness of its applications especially for high frame-rate/fill-factor quantum imaging and ranging systems [6]- [8], [16]- [22].…”

Random Sampling-and-Averaging with Variance-Reduction Techniques in Quantum Measurements

“…It can be easily proven that Var[Y] = Var[Q], and Var[Y] = Var[Q] = P 1 ÁP 0 /N DCO as expressed in Eq. (7). When only the quantization noise power (i.e., Var[Q ]) is considered, the effective number of binary bits (ENOB) of the RSA technique can be expressed as [6]:…”

“…In the case of OSR = 1, the probability of obtaining a Logic-1 per sample is exactly τ/T = P 1 , so the expectation and theoretical variance of each RSA measurement are equal to the results shown in Eqs. ( 6) and (7), respectively. In the cases of OSR < 1 (i.e., subsampling), for example, when OSR = 1/4, the sampling region of each CK DCO edge is extended to 4ÁT, the probability of obtaining a Logic-1 stays the same as τ/T = (4Áτ)/(4ÁT) = P 1 since the positive duty-cycle of CKτ is also extended by 4 times.…”

“…(b) t SAMP,n is the n-th absolute time at the n-th sampling edge of the DCO. (c) ΔT PRBS,n is the n-th DCO period dynamically extended by the PRBS generator (T DCO,n =T DCO,MIN + ΔT PRBS,n ) between (T DCO,MIN + 0) and (T DCO, MIN + ΔT PRBS,MAX ) [7]. Both T DCO,MIN and ΔT PRBS,MAX can be coarsely adjusted by their own static controls in the DCO circuit.…”