An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication

Kwon, Woocheol; Hong, Sun-Gi; Yoo, Sungjoo; Min, Byeong; Choi, Kyu-Myung; Eo, Soo-Kwan

doi:10.1109/date.2008.4484849

Cited by 1 publication

(2 citation statements)

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“…A predictive flow controller that controls the packet injection rate is proposed in [14]. To improve the overall execution time and link utilization, optimal link scheduler and shared buffer router architecture are proposed in [15]. An open-loop flow control scheme is proposed in [16] to reduce the conflicts of data transfers from multiple memory modules to the same masters.…”

Section: Related Workmentioning

confidence: 99%

“…Indeed, based on our idea, any deterministic and adaptive routing scheme can be combined to form our SDRAMaware router. Another flow-control mechanism mentioned in section 2 can also be combined to avoid deadlock and livelock [17], to make traffic load balanced on a network [12][13][14] and to manage buffers and channel bandwidth [15].…”

Section: Sdram-aware Noc Routermentioning

confidence: 99%

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An SDRAM-Aware Router for Networks-on-Chip

Jang

Pan

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory latency. Moreover, our multi-scheduling scheme performed by the multiple SDRAM-aware routers helps to achieve better SDRAM performance and save the hardware cost of NoC platform. Experimental results show that our SDRAMaware router improves memory latency by 18% and memory utilization by 4.9% on average with over 42% saving of gate count of the NoC platform with dual memory subsystem.

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Section: Related Workmentioning

confidence: 99%