An optimal allocation of memory buffers for complex multicore platforms

Goens, Andrés; Castrillón, Jerónimo; Odendahl, Maximilian; Leupers, Rainer

doi:10.1016/j.sysarc.2016.05.002

Cited by 7 publications

(5 citation statements)

References 6 publications

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“…This works well for the selected application model, which, however, necessitates large amounts of data copying and is therefore inherently inefficient on shared memory platforms [35]. Finally, Goens et al [13] employ a buffer allocation approach similar to this paper. While they use a more general platform model and a more detailed application model, this comes at the price of longer optimisation time (hours as compared to milliseconds).…”

Section: Related Workmentioning

confidence: 94%

Minimising Access Conflicts on Shared Multi-Bank Memory

Tretter

Giannopoulou

Baer

et al. 2017

ACM Trans. Embed. Comput. Syst.

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A common multi-core pattern consists of processors communicating through shared, multi-banked on-chip memory. Two approaches exist: Interleaved address mapping, which spreads consecutive data over all banks, and contiguous address mapping, which stores consecutive data on a single bank. In this work, we compare both approaches on the Kalray MPPA-256 platform. For contiguous mapping, we propose an algorithm, based on graph colouring techniques, to automatically perform the assignment of data blocks to memory banks with the goal of minimising access collisions and delays. Experiments with representative, parallel real-world benchmarks show that 69% of the tested configurations, when optimised for contiguous mapping by our algorithm, run up to 86% faster on average than with interleaved mapping. CCS Concepts: • Computing methodologies → Shared memory algorithms; • Computer systems organization → Embedded software; System on a chip; • Hardware → Memory and dense storage;

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Section: Related Workmentioning

confidence: 94%

Minimising Access Conflicts on Shared Multi-Bank Memory

Tretter

Giannopoulou

Baer

et al. 2017

ACM Trans. Embed. Comput. Syst.

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“…In other recent works, which also consider memory configuration, both deterministic and meta-heuristic approaches are used to solve the task mapping problem. Integer linear programming (ILP) is a popular example of a deterministic strategy, used in [ 8 , 15 , 18 , 19 ]. A comprehensive approach, focusing on integrating memory allocation into the DSE, is found in the following papers.…”

Section: Related Workmentioning

confidence: 99%

“…Goens et al. [ 19 ] use Mixed Integer Programming (MILP) to optimize memory allocation on a heterogeneous platform. Again, the data allocation scheme in memory is generated after assigning tasks to processors.…”

Section: Related Workmentioning

confidence: 99%

Design Space Exploration of Clustered Sparsely Connected MPSoC Platforms

Frid

Sruk

Jakobović

2022

Sensors

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Heterogeneous multiprocessor platforms are the foundation of systems that require high computational power combined with low energy consumption, like the IoT and mobile robotics. In this paper, we present five new algorithms for the design space exploration of platforms with elements grouped in clusters with very few connections in between, while these platforms have favorable electric properties and lower production costs, the limited interconnectivity and inability of heterogeneous platform elements to execute all types of tasks, significantly decrease the chance of finding a feasible mapping of application to the platform. We base the new algorithms on the Non-dominated Sorting Genetic Algorithm II (NSGA-II) meta-heuristic and the previously published SDSE mapping algorithm designed for fully interconnected multiprocessor platforms. With the aim to improve the chance of finding feasible solutions for sparsely connected platforms, we have modified the parts of the search process concerning the penalization of infeasible solutions, chromosome decoding, and mapping strategy. Due to the lack of adequate existing benchmarks, we propose our own synthetic benchmark with multiple application and platform models, which we believe can be easily extended and reused by other researchers for further studying this type of platform. The experiments show that four proposed algorithms can find feasible solutions in 100% of test cases for platforms with dedicated clusters. In the case of tile-like platforms, the same four algorithms show an average success rate of 60%, with one algorithm going up to 84%.

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“…Sánchez-Oro et al [20] proposed a parallel variable neighborhood search algorithm for the dynamic memory allocation problem to solve dynamic memory allocation problems in embedded systems. Goens et al [21] modeled the application in a data-centric way, by explicitly defining buffers and associating computational tasks that access the buffers within well-specified time intervals, and then presented a layered approach to describe and solve the buffer-allocation problem as well as related subproblems, using mixed-integer linear programming. Soto et al [22] proposed two midterm iterative approaches to solve a static version of the allocation problem, which have the best solution quality compared to long-term and short-term approaches.…”

Section: Introductionmentioning

confidence: 99%

“…Based on the full-time spectrum theory [21], time operator T k ⊆ T is introduced to represent time frame in blocks, so all time dependencies can be handled at once instead of a single time point. To ensure that data flow is efficient, for all edges e ′ ∈ E ′ , the amount of data cannot exceed the bandwidth at any time point.…”

mentioning

confidence: 99%

Wireless Sensor Network Deployment in Cyberphysical Machine Tool System Based on Optimal Allocation of Memory Buffers

Zhou

2021

Journal of Sensors

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As an important direction of Industry 4.0, cyberphysical machine tool systems (CPMTS) can realize the deep integration and real-time interaction of physical components and information to optimize manufacturing processes. Wireless sensor network (WSN), an important part of CPMTS, is responsible for data collection and transmission. However, in the process of data transmission, due to memory limitations and noise interference, unreasonable sensor distribution will affect the performance of CPMTS. At the same time, data accuracy will be affected due to the resource constraints of CPMTS. To solve the problems above, this paper firstly presented a single-station transfer model to ensure the layout of sensors in each sink, which can meet the detection capability of fault/monitoring data. Then, by using fuzzy graphs, a multihop-station transfer model and data-collecting model are developed to describe the data flow and memory allocation in the wireless network. Taking noise interference and data position into consideration, a MILP problem is formulated and the optimization solution is obtained by using the “branch and bound” method. Finally, case studies about optimal sensor distribution on the single station and path optimization on the multihop station are presented to illustrate the proposed strategy. The case studies validated that the proposed sensor distribution in a single station can achieve higher detectability with fewer resources, and the optimization path strategy can achieve the best performance in two proposed experiments, compared to the shortest path and noninferior path strategies.

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An optimal allocation of memory buffers for complex multicore platforms

Cited by 7 publications

References 6 publications

Minimising Access Conflicts on Shared Multi-Bank Memory

Minimising Access Conflicts on Shared Multi-Bank Memory

Design Space Exploration of Clustered Sparsely Connected MPSoC Platforms

Wireless Sensor Network Deployment in Cyberphysical Machine Tool System Based on Optimal Allocation of Memory Buffers

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