An Optimal Machine Learning Classification Model for Flash Memory Bit Error Prediction

Fitzgerald, Barry; Ryan, Conor; Sullivan, Joseph A.

doi:10.1007/978-3-030-02357-7_5

Cited by 2 publications

(1 citation statement)

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“…Previous works by the authors have developed prediction models based on data collected at the rated endurance, to determine how much further each sector could be cycled before exceeding an RBER threshold [3], [5], [6]. Sector errors, program time and erase time were all found to have predictive value for this purpose.…”

Section: Related Researchmentioning

confidence: 99%

An Early-Life NAND Flash Endurance Prediction System

Fitzgerald¹,

Ryan

Sullivan

2021

IEEE Access

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NAND flash memory -ubiquitous in today's world of smart phones, SSDs (solid state drives), and cloud storage -has a number of well-known reliability problems. NAND data contains bit errors, which require the use of error correcting codes (ECCs). The raw bit error rate (RBER) increases with programerase (P-E) cycling, and the number of P-E cycles the device can withstand before the RBER exceeds the ECC capability is called its endurance. ECC operates on data stored in a sector of NAND, and there is a large variation in the endurance of sectors within a device and across devices, resulting in excessively conservative endurance specifications. This research shows, for the first time, that a sector's true endurance can be predicted with remarkable accuracy, using a combination of the sector's location within the device, and measurements taken at the very beginning of life. Real-world data is gathered on millions of NAND sectors using a custom-built test platform. Optimised machine learning classification models are built from the raw data to predict if a sector will pass or fail to a fixed ECC threshold, after a target P-E cycling level has been reached. A novel technique is demonstrated that uses different ECC thresholds for model training and testing, which allows the models to be tuned so that they never misclassify samples that would fail. This eliminates ECC failures and data loss, allowing simpler, less expensive ECC schemes to be used for modern NAND devices. It also enables significant endurance extensions to be achieved.

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Section: Related Researchmentioning

confidence: 99%