An optimal memory allocation scheme for scratch-pad-based embedded systems

Abstract

This article presents a technique for the efficient compiler management of software-exposed heterogeneous memory. In many lower-end embedded chips, often used in microcontrollers and DSP processors, heterogeneous memory units such as scratch-pad SRAM, internal DRAM, external DRAM, and ROM are visible directly to the software, without automatic management by a hardware caching mechanism. Instead, the memory units are mapped to different portions of the address space. Caches are avoided due to their cost and power consumption, and because they make it difficult to guarantee real-time performance. For this important class of embedded chips, the allocation of data to different memory units to maximize performance is the responsibility of the software.Current practice typically leaves it to the programmer to partition the data among different memory units. We present a compiler strategy that automatically partitions the data among the memory units. We show that this strategy is optimal, relative to the profile run, among all static partitions for global and stack data. For the first time, our allocation scheme for stacks distributes the stack among multiple memory units. For global and stack data, the scheme is provably equal to or better than any other compiler scheme or set of programmer annotations. Results from our benchmarks show a 44.2% reduction in runtime from using our distributed stack strategy vs. using a unified stack, and a further 11.8% reduction in runtime from using a linear optimization strategy for allocation vs. a simpler greedy strategy; both in the case of the SRAM size being 20% of the total data size. For some programs, less than 5% of data in SRAM achieves a similar speedup.

An integrated scratch-pad allocator for affine and non-affine code

“…These include the static allocation described in [3] and the dynamic method for non-affine programs [10]. We also consider three variations of an affine-only method that only handles affine loops, flushing the SPM after each loop.…”

Data cache organization for accurate timing analysis

“…This program managed memory implies a more complicated programming model. However, scratchpad memory can be automatically partitioned [3,1,49]. A similar approach for time-predictable caching is to lock cache blocks.…”

“…Full associativity is expensive in terms of hardware, and therefore the size of this cache is limited to 16 or 32 cache lines. [3] hit [3] dout [3] cache …”

Optimizing Local Memory Allocation and Assignment through a Decoupled Approach

“…It paritions the LM for each different array size, performs live range spliting and use a register allocation framework to perform memory coloring. The second approach [16,17,24] allocates data onto the scratch-pad memory between program regions separated by specific program points. More specifically, allocation is based on the access frequency-per-byte of a variable in a region (collected from profile data).…”