An optimized design of binary comparator circuit in quantum computing

Sarker, Ankur; Amin, Mohammad; Bose, Avishek; Islam, Nafisah

doi:10.1109/iciev.2014.6850768

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…With the continuous improvement of technology, higher requirements for the commemorative significance of traditional surprise boxes are required [3] [4]. The application of high-tech technology to surprise box will determine the new trend and prospects of surprise box development.…”

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confidence: 99%

A New Method for Surprise Box Quantity Determination Based on Comparer

Yang,

Jing,

Liang

et al. 2024

IEEE Access

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To address the limitation of traditional surprise boxes that only support single or fixed quantity customization, this paper proposed a new method: utilizing comparators to detect cascaded quantities for specific customization. This innovative approach aims to simplify the customization process of surprise boxeswhileavoidingthecomplexityofusingmicro-controllersforquantitydetermination.Adualcomparatoris employed to compare the results that are greater or smaller than the set quantity . Then the output of the dual comparator is connected to an AND gate circuit,triggering the hidden function of the central surprise box when the AND gate generates high levels . The system design involves setting the number of surprise boxes and connecting upperandlowerlimitcomparators tothecurrent surprise boxconnection signal.Byselecting thesize of the cascade resistor , the number of surprise boxes can be determined . This paper provides step -by-step instructions for calculating the cascade resistor.Furthermore,the proposed method'sreliability indetermining thenumberofsurprise boxesisdemonstrated bysettingthenumberofsecondary surprise boxestosevenandfour , with the allowed resistance error 6.4% and 11%, respectively . The results indicate that a higher number of connected surprise boxes leads to a smaller range of cascaded resistors and higher accuracy requirements . Through these case studies ,it has been verified that the design using dual comparators can achieve the desired quantity detection , and the detection circuit exhibits a high degree of redundancy in resistance value error , resultinginincreasedreliabilityofthedetectionresults.

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confidence: 99%

A New Method for Surprise Box Quantity Determination Based on Comparer

Yang,

Jing,

Liang

et al. 2024

IEEE Access

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“…In this chapter, we will summarise our proposed quantum comparator circuit to Cuccaro's comparator, VBE comparator, and ripple carry comparator generalised from (Sarker et al, 2014;Oliveira et al, 2006;Beckman et al, 1996). The result we compared were not from their original papers but rather their implementation on Table 5.1: Circuit cost summary for n ≥ 3.…”

Section: Resultsmentioning

confidence: 99%

“…Second approach to building quantum comparator is to directly design sub circuit to compare each bit of the number similar to classical ripple comparator approach. Most literature on this approach were done with the aim of optimising quantum cost (Beckman et al, 1996;Sarker et al, 2014;Oliveira et al, 2006). No literature on this approach which focus on optimising C-Not can be found.…”

Section: Quantum Comparatormentioning

confidence: 99%

Quantum comparator circuit on superconducting quantum computer

Benchasattabuse

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In this thesis, we present an optimised quantum comparator circuit based on Cuccaro's ripple-carry quantum adder using relative phase techniques from Maslov's multiple control Toffoli optimisation. We extend the cost function from simply counting C-Not and Toffoli gate to Qiskit cost which defines arbitrary single qubit gate cost as unity and C-Not as the only two qubit gate cost as ten. We report the comparison result between our comparator circuit with previous comparator circuits from literature using optimal Toffoli implementation with Qiskit cost, C-Not count, and circuit depth. We also report our experiment of implementing a two-bit comparator on IBM QX devices.

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1-bit Magnitude Comparator based on ReversibleLogic using QCA Technology

Dhare

Modi

2023

2023 IEEE Devices for Integrated Circuit (DevIC)

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An optimized design of binary comparator circuit in quantum computing

Cited by 4 publications

References 8 publications

A New Method for Surprise Box Quantity Determination Based on Comparer

A New Method for Surprise Box Quantity Determination Based on Comparer

Quantum comparator circuit on superconducting quantum computer

1-bit Magnitude Comparator based on ReversibleLogic using QCA Technology

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