An Optimized FPGA Based System Design for the Arrhythmia Detection using ECG

Abstract

Electrocardiogram signals are highly susceptible to interferences caused due to various kinds of noises including artefacts’, disruptions in power lines attained from the human interferences and device disturbances. These noise signals tend to lower the quality of signals that result in crucial environment for detecting and diagnosing different types of arrhythmia. In order to avoid this issue, multiple filtering techniques are being incorporated out of all Gaussian filters with Haar DWT portray better outcomes in noise elimination and smoothening of signal. The process of ECG signal filtering allows performing the testing and validation of in the actual world emulation. Enhancement in PSNR ratio is observed by using the ECG signal filters along the reconstructed signal. For a given input ECG signal, the levels of the signal peak decide if the patient is suffering from arrhythmia or not. If peak is low, patient is detected with the arrhythmia disease, if high patient is normal. The results can be observed in simulation. FPGA prototyping of the design is carried out along the hardware debugging in chip scope pro tool. The design is realized using Verilog coding with the technique of morphological filtering. For the purpose of debugging the hardware device used is Artix-7. The FPGA methodology is success full in a position to detect arrhythmia. The framework based on FPGA is structured and executed in the paper which can detect a type of arrhythmia which indicates Atrio Ventricular block along with all the noises removed. The simulation results are obtained by taking ECG signals from MIT-BIH arrhythmia database. The proposed FPGA based system design is proven to be optimized as it showed very less utilization of resources when compared to previous arrhythmia detection system designs.