An Optimized Implementation of Activation Instruction Based on RISC-V

Abstract

Activation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V processor Hummingbird E203, we designed a special instruction for the implementation of activation functions. A single instruction is chosen to implement the entire activation operation, including data loading, data arithmetic and data write-back. At the hardware level, we designed a method of alternate reading and writing that only needs a small hardware storage unit to meet the requirements of the activation operation for long arrays without affecting the activation efficiency. In addition, we added the length of the array as a new parameter to instruct our designed hardware to adapt to any length of arrays. Finally, the scheduling method of some instructions in the activation process was optimized in accordance with the law of instructions, which improves the execution efficiency of instructions. Considering an activation process with an array length of 15, our design demonstrates a 4.89-fold increase in speed compared to RISC-V standard instructions while consuming only 7.78% of the energy.

A Survey on IEEE 1588 Implementation for RISC-V Low-Power Embedded Devices

“…Additionally, RISC-V adheres to a coherent and sequentially consistent memory model, simplifying programming and code porting across various implementations. Moreover, the architecture offers the possibility of optimization for low power consumption by selecting suitable extensions and configurations [11].…”