An optimized reconfigurable architecture for hardware implementation of decimal arithmetic

Emami, Samaneh; Sedighi, Mehdi

doi:10.1016/j.compeleceng.2017.08.018

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…Most works on decimal multiplication target ASICs, but several architectures have been proposed for FPGA and coarse-grained reconfigurable computing [38]. Any of the previous architectures can be directly mapped to FPGA.…”

Section: Related Workmentioning

confidence: 99%

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Véstias

Neto

2021

Algorithms

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Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

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Section: Related Workmentioning

confidence: 99%

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Véstias

Neto

2021

Algorithms

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“…The DPR concept may also be used in applications and systems where latency is considered as one of the prime factors to determine the system's performance. Various processor design styles [23,24] may be implemented in runtime that will have a significant impact in terms of execution time-thereby on performance of a specific program, as discussed in this work.…”

Section: Dynamic Partial Reconfigurationmentioning

confidence: 99%

An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

et al. 2019

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Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.

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An optimized reconfigurable architecture for hardware implementation of decimal arithmetic

Cited by 2 publications

References 8 publications

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

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