An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

Radens, C.; Kudelka, S.; Nesbit, L.; Malik, R.; Dyer, T.; Dubuc, Christian; Joseph, Thomas; Seitz, Michelle E.; Clevenger, L. A.; Arnold, N.; Mandelman, J.; Divakaruni, R.; Casarotto, D.; Lea, D.; Jaiprakash, V.C.; Sim, Jae Sung; Faltermeier, J.; Low, Kain Lu; Strane, J.; Halle, Scott; Ye, Q.; Bukofsky, S.; Gruening, U.; Schloesser, T.; Bronner, G.

doi:10.1109/iedm.2000.904327

Cited by 5 publications

(4 citation statements)

References 1 publication

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“…Applying a self-aligned contact to memory cells is essential to reduce the cell area despite the speed penalty inflicted by the increased contact resistance. Leading developments of standalone DRAM cells in research and development are a 6-4F 2 trenchcapacitor vertical-MOSFET cell [33,34] and a 6F 2 stacked-capacitor open-DL cell [35]. Here, the open-DL cell necessitates a low-impedance array to suppress inherent array noises [4,36] generated by imbalances between a pair of DLs, each of which is placed in different subarrays.…”

Section: One-transistor Cells For Standalone Dramsmentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

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Section: One-transistor Cells For Standalone Dramsmentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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“…Static RAM (SRAM) [1][2][3][4][5][6][7][8][9][10] and dynamic RAM (DRAM) [11][12][13][14][15][16][17][18][19][20] (conventional volatile memories) suffer from significant leakage power and flash memory [21][22][23][24][25][26][27][28][29][30] (conventional non-volatile memories (NVMs)) suffers from high write power and poor endurance/ performance. However, emerging NVMs can be beneficial since they offer zero leakage and high scalability, density, and endurance [31].…”

Section: Introductionmentioning

confidence: 99%

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Khan

Ghosh

2021

JLPEA

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Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

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“…Present DRAM chips in production integrate a 1-transistor, 1-capacitor (1T/1C) cell having an area of 8 [1]. Experimental 1T/1C cells having an area of 6 or even 4 have been proposed [2], [3], but for all 1T/1C cells, the main challenge in cell area reduction lies with the capacitor integration. Indeed for each memory generation, a constant capacitance value of 30 fF/cell is targeted [4].…”

Section: Introductionmentioning

confidence: 99%

A capacitor-less 1T-DRAM cell

Okhonin

Nagoga

Sallèse

et al. 2002

IEEE Electron Device Lett.

214

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A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states. This cell is two times smaller in area than the conventional 8 2 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.

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An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

Cited by 5 publications

References 1 publication

Review and future prospects of low-voltage RAM circuits

Review and future prospects of low-voltage RAM circuits

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

A capacitor-less 1T-DRAM cell

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