An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS

Chiu, Pi-Feng; Celio, Christopher; Asanović, Krste; Patterson, David A.; Nikolić, Borivoje

doi:10.1109/vlsic.2018.8502320

Cited by 8 publications

(3 citation statements)

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“…Chipyard has the distinct advantage that it allows us to freely configure SoCs based on either an in-order (Rocket [4], CVA6 [11] Ibex [8] and an educational core called Sodor) or out-of-order (BOOM [35]) core or even mix both. For example, we can add or remove caches and change their size or modify aspects of the cores themselves, such as the number of issues in the BOOM core, the size of the return order buffer, and much more.…”

Section: B How Risc-v Supports Research In System-level Testmentioning

confidence: 99%

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

Anders,

Andreu,

Becker

et al. 2023

2023 IEEE European Test Symposium (ETS)

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With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.

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Section: B How Risc-v Supports Research In System-level Testmentioning

confidence: 99%

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

Anders,

Andreu,

Becker

et al. 2023

2023 IEEE European Test Symposium (ETS)

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show abstract

“…Block or subblock-level disabling and remapping techniques were also proposed in [36] and [37]. A recent implementation of RISC-V processor employs a line recycling technique [38] that combines three faulty cache lines which are recycled to compose one non-faulty cache line. The above mentioned disabling-based techniques could be used when the process variation severity is low.…”

Section: Related Workmentioning

confidence: 99%

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Kong

Hur

2020

IEEE Access

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Near-threshold computing (NTC) has recently emerged and been considered as a strong candidate for future energy-efficient computing. However, adverse impacts from process variation such as delay and power fluctuations within die as well as across dies are much more severe than the super-threshold regime. In particular, static random access memory (SRAM)-based components (e.g., cache memories) are easily affected by process variation in NTC, resulting in large delay fluctuations. It incurs a huge loss in the maximum clock frequencies of processors, which eventually leads to huge yield losses. In this paper, we first analyze L1 data cache yield in NTC and reveal an inefficiency of frequency binning for yield improvement in NTC. We then introduce a variable latency L1 data cache for NTC to obtain a sufficient yield. By allowing the higher cache access cycles, we can improve cache yield with only a little performance overhead. Moreover, we propose an adaptive line migration technique which improves performance and energy efficiency of variable latency caches. The cache line which is expected to be frequently accessed in the near future is dynamically migrated to the fastest way in a cache set. According to our evaluation, our cache architecture greatly improves cache yield with only a little performance, energy, and area overhead.

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“…However, the number of redundancy sub-blocks in a cache set is fixed, which is not flexible enough for different scenarios. Chiu et al [16] presented a scheme called line recycling that using three disabled weak cachelines to recycle one useable cacheline. Although one third disabled weak cachelines can be recycled in their approach, over half of the disabled cachelines are wasted, not mention the energy consumption of the three cachelines reading for one recycled cacheline and extra hardware overhead.…”

Section: B the Cache Architecturementioning

confidence: 99%

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

et al. 2019

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The probability of timing failure in SRAM accessing becomes unacceptably high at low voltages, which makes the SRAM become the bottleneck of the system performance. Recently proposed timing speculation SRAM (SSRAM) can access bit cells much earlier than the conservative time margin and detect the potential timing failures. Unfortunately, the performance benefit brought by this speculative scheme might be nullified by the extra cycles used to correct the errors. Therefore, in a cache architecture, cachelines containing bit cells with timing failure bring significant performance degradation in a low-voltage scenario. In this paper, we propose the set-associative L1 and L2 Remapping and Reuse-aware timing Speculation caches (RRS caches) based on the cross-sensing SSRAM to reduce the weak cacheline access penalties under low supply voltages. RRS caches improve the proportion of the error-free cachelines (or strong cachelines) by clustering as more as possible bit cells with timing failures into weak cachelines. In addition, RRS caches swap the frequently reused data to the error-free cachelines to further reduce the average access latency and the energy consumption by an optimized filling/replacement policy. We compared the performance, energy consumption and area overhead of RRS caches with those of state-of-the-art approaches. According to our simulation results, RRS caches improve the system performance close to that of the Perfect caches in a four-core processor with only 0.12% extra energy consumption, 4.12% extra area overhead in the L1 cache and 2.69% extra energy consumption, 5.66% extra area overhead in the L2 cache compared to the cache designs with the raw SSRAM. INDEX TERMS Cacheline remapping, low-voltage cache, near-threshold voltage, replacement policy, timing speculation SRAM.

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An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS

Cited by 8 publications

References 0 publications

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

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