An overview of RISC architecture

Abstract

Computer architecture designs are usually based on historical data, and the development of computers has been influenced by three factors: market (users), software and hardware methods, and technology. Of the three factors, technology is the most dominant. The reduced instruction set computer (RISC) has emerged as a formidable competitor to the conventional, complex instruction set computer (CISC), systems. The emergence of RISC was a direct result of advances in technology and historical data collected on how instruction sets are used by compilers. Advances in very large scale integration and compilers are enabling RISC architecture to exploit parallelism in systems that are conventional sequential in their mode of operation. The second generation of RISC processors are utilizing superpipelining or superscalar to achieve execution speed that was once attainable only on mainframes and supercomputers. Future RISC processors will use both superscalar and superpipelining techniques to achieve speed beyond the 50 MIPS that is attainable on some of today's processors.