An SEU-hardened ternary SRAM design based on efficient ternary C-elements using CNTFET technology

Bakhtiary, Vahid; Amirany, Abdolah; Moaiyeri, Mohammad Hossein; Jafari, Kian

doi:10.1016/j.microrel.2022.114881

Cited by 17 publications

(6 citation statements)

References 47 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also, the SNM of the proposed SRAM is 36.36% higher than the highest SNM of other designs under consideration. The design of ternary logic using CNTFET is more prolific than other well technologies due to the ease of adjusting the threshold voltage [54,55]. The CNTFET technology offers ballistic transport [56], very little surface scattering, minimum leakage current, and parasitic effects [58].…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

show abstract

Section: Resultsmentioning

confidence: 99%

“…The cell optimizes the power consumption but has less stability during the hold mode of operation. The design of ternary logic using CNTFET is more prolific than other well technologies due to the ease of adjusting the threshold voltage [54,55]. The CNTFET technology offers ballistic transport [56,57]…”

Section: Literature Survey On Cntfet-based Tsrammentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

show abstract

“…By restricting both weights and activations to 1-bit precision, the system circumvents the necessity for complex and error-prone floatingpoint operations, which demand high levels of precision and stability in electronic systems. [59][60][61][62][63][64][65][66][67][68][69][70][71][72] This co-design strategy streamlines the optical realizations of computational tasks associated with BNNs. Optical components inherently suited for binary operations, like the XNOR gate, become pivotal in this architecture, facilitating efficient and accurate computations by directly manipulating the properties of light.…”

Section: Proposed Optical Binary Neural Network Acceleratormentioning

confidence: 99%

An efficient optical-based binary neural network hardware accelerator for harsh environments

Jahannia,

Ye,

Altaleb

et al. 2024

Silicon Photonics XIX

View full text Add to dashboard Cite

Binarized neural networks offer substantial reductions in memory and computational requirements compared to full precision networks. However, conventional CMOS-based hardware implementations still face challenges with resilience for deployment in harsh environments like space. This paper proposes an optical XOR-based accelerator for binarized neural networks to enable low power and resilient operation. The optical logic gates rely on wavelength-specific intensity propagation rather than absolute intensity levels. This provides inherent robustness against fabrication process variations and high energy particle strikes. Simulations of an optical hardware prototype for XNOR-Net show the accelerator achieves 1.2 µs latency and 3.2 mW power. The binarized network maintained 2-4% accuracy degradation compared to the full precision baseline on MNIST and CIFAR-10. The proposed optical accelerator enables efficient and resilient deployment of binarized neural networks for harsh environment applications like spacecraft and satellites.

show abstract

“…[55][56][57][58][59][60][61][62] Flash memory, while ubiquitous in current devices, struggles with issues related to endurance, power consumption, and performance degradation as memory cells are scaled down in size. [63][64][65][66][67] In contrast, PCM offers a viable and attractive alternative. Its improved endurance and non-volatility ensure that data integrity is maintained over extensive periods without the need for constant power supply, a crucial feature for batteryless IoT devices operating in remote or difficult-to-access areas.…”

Section: Phase Change Memorymentioning

confidence: 99%

Optical memory in IoT devices: an energy-efficient approach using phase change materials

Jahannia,

Ye,

Altaleb

et al. 2024

AI and Optical Data Sciences V

View full text Add to dashboard Cite

As Internet-of-Things (IoT) devices continue to grow rapidly in number, developing energy-efficient memory solutions has become critically important. This paper introduces an innovative Phase Change Memory (PCM) architecture that can significantly reduce memory energy consumption in IoT devices. After highlighting the energy-inefficiency of current memory designs, we explore the possibilities of leveraging PCM. We demonstrate that the benefits of exploiting PCM are dependent on the working frequency of the CPU and show how PCM can surpass devices with SRAM and DRAM. As a replacement candidate for FLASH, PCM can also be utilized instead of SRAM and DRAM. We also demonstrate that, based on the application, we can also save more energy. Ongoing work focuses on deployment of this application dependency and enhancing energy efficiency of devices using PCM. This represents a major advance towards realizing widespread integration of photonics and electronics in IoT hardware.

show abstract

An SEU-hardened ternary SRAM design based on efficient ternary C-elements using CNTFET technology

Cited by 17 publications

References 47 publications

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

An efficient optical-based binary neural network hardware accelerator for harsh environments

Optical memory in IoT devices: an energy-efficient approach using phase change materials

Contact Info

Product

Resources

About