An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM

Weaver, H. T.; Axness, Carl L.; McBrayer, J. D.; Browning, J.S.; Fu, J.S.; Ochoa, A.; Koga, R.

doi:10.1109/tns.1987.4337466

Cited by 54 publications

(15 citation statements)

References 11 publications

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“…Such a classic cell consists in a couple of two inverters, their outputs connected to the input of each other. The first approach to mitigate SEUs was to include resistors between the output and the input of the inverters [41]. This is equivalent to add an LP filter to the structure so the penalty is that the IC speed plunges down.…”

Section: B Mitigation By Designmentioning

confidence: 99%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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Abstract-New generation electronic devices have become more and more sensitive to the effects of the natural radiation coming from the surrounding environment. These radiation sources are cosmic rays and radioactive impurities, able to corrupt the content of memory cells or to induce transient pulses in combinational logic. The growing sensitivity seems to be related to two main factors: the lower and lower charge needed to define the logic levels in advanced devices and the increasing number of basic components inside the modern integrated circuits. In this paper, are described state-of-art techniques to mitigate these effects as well as typical tests to verify the radiation-tolerance of the devices and/or systems.

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Section: B Mitigation By Designmentioning

confidence: 99%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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“…This event is referred to as Single Event Upset (SEU) [11] in a latch circuit. For example, if a latch is storing logic ‗1', the NMOS corresponding to the latch is susceptible to SEU, because the body voltage is 0 Volt and drain is at logic '1'.…”

Section: Effects Of Radiations On Mosfets and Cntfetsmentioning

confidence: 99%

Set and Seu Analysis of Cntfet Based Designs in Harsh Environments

Chavan¹,

Reddy²

2014

IJRET

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“…One of the earliest, and most successful, techniques for hardening CMOS latches is resistor hardening [88]. As shown in Figure 1.27 a resistor is placed in the feedback path of the latch forms a low-pass filter.…”

Section: Seu-resistant Latch Circuitsmentioning

confidence: 99%

Magnetic Random Access Memory for Embedded Computing

Donohoe¹

2007

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Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing this collection of information. MRAM_II_2007-Final SPONSORING / MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR'S ACRONYM(S)Air Force Research Laboratory AFRL/RVSE Space Vehicles Directorate 3550 Aberdeen Ave. SE SPONSOR/MONITOR'S REPORTKirtland AFB, NM 87117-5776 NUMBER(S) AFRL-RV-PS-TR-2007-1196 DISTRIBUTION / AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. (Clearance #VS07-0688) SUPPLEMENTARY NOTESThis report is published in the interest of scientific and technical information exchange. The established procedures for editing reports were not followed for this technical report. ABSTRACTThe goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide largescale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory. ii University of Idaho report MRAM_II_2007-Final SUBJECT TERMS CMOS, MTJ Cell

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An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM

Cited by 54 publications

References 11 publications

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Set and Seu Analysis of Cntfet Based Designs in Harsh Environments

Magnetic Random Access Memory for Embedded Computing

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