An SRAM PUF with 2 Independent Bits/Cell in 65nm

Shifman, Yizhak; Miller, Avi; Weizman, Yoav; Fish, Alexander; Shor, Joseph

doi:10.1109/iscas.2019.8702612

Cited by 9 publications

(4 citation statements)

References 6 publications

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“…In contrast to Lu Lu et al's proposed sequence-dependent SRAM PUF, which employs a conventional SRAM 6T transistor structure [27], Shifman Y et al approach utilizes two cells to generate one bit of data. The resulting data is determined by the length and arrangement of the sequence [26]. Specifically, for an array with m rows and n columns, the number of CRPs can be calculated as follows, given a sequence length of r:…”

Section: B Research Work Related To Ecc Associated With Pufmentioning

confidence: 99%

A Highly Reliable Reconfigurable SRAM PUF Based on Error Correction Codes and Capacitor Preselection

Yuyuan,

Xueqiang

2024

Preprint

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In recent years, researchers have extensively utilized the inherent variations occurring during the manufacturing process of integrated circuits to create physical unclonable functions (PUFs) as hardware security primitives. However, traditional static entropy sources employed in PUF applications exhibit certain drawbacks, including limited availability of challengeresponse pairs (CRPs) and inadequate randomness. Additionally, the reliability of PUFs is compromised due to the impact of temperature and voltage fluctuations as well as aging effects. To address these issues, this article presents a novel architecture for PUFs based on Static Random Access Memory (SRAM) along with a more suitable error-correcting code (ECC). Our approach enhances the reliability of SRAM-based PUFs both internally, through capacitor preselection, and externally, by employing ECC. The coding and decoding process of the ECC is elaborated in detail. Furthermore, we analyze the relevant parameters of the ECC and demonstrate that the combination of these techniques results in a final bit error rate (BER <0.1%). Through calculations, we validate that our reconfigurable SRAM PUF can yield a larger number of CRPs. Experimental results conducted on Xilinx Artix 7 demonstrate that the ECC we employ achieves an ideal BER for PUFs, while simultaneously reducing hardware overhead by 80%.

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Section: B Research Work Related To Ecc Associated With Pufmentioning

confidence: 99%

A Highly Reliable Reconfigurable SRAM PUF Based on Error Correction Codes and Capacitor Preselection

Yuyuan,

Xueqiang

2024

Preprint

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“…SRAM cells are resistant to circuit degradation and can be used to build reliable SRAM based PUFs which can be used for authentication and secret key generation [ 62 , 63 , 64 ]. Huang and Wang [ 36 ] have shown that PUF can be utilized for identity verification in order to secure IoT hardware via device authentication.…”

Section: Hardware Assisted Security Of Fog Computing Devicesmentioning

confidence: 99%

Hardware Security of Fog End-Devices for the Internet of Things

Bütün

Sari

Österberg

2020

Sensors

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The proliferation of the Internet of Things (IoT) caused new application needs to emerge as rapid response ability is missing in the current IoT end-devices. Therefore, Fog Computing has been proposed to be an edge component for the IoT networks as a remedy to this problem. In recent times, cyber-attacks are on the rise, especially towards infrastructure-less networks, such as IoT. Many botnet attack variants (Mirai, Torii, etc.) have shown that the tiny microdevices at the lower spectrum of the network are becoming a valued participant of a botnet, for further executing more sophisticated attacks against infrastructural networks. As such, the fog devices also need to be secured against cyber-attacks, not only software-wise, but also from hardware alterations and manipulations. Hence, this article first highlights the importance and benefits of fog computing for IoT networks, then investigates the means of providing hardware security to these devices with an enriched literature review, including but not limited to Hardware Security Module, Physically Unclonable Function, System on a Chip, and Tamper Resistant Memory.

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“…The authors have also demonstrated an improvement of nearly 2X to the area of the SRAM-based PUF by sharing some of the PUF transistors, such that two independent bits are generated by each cell [15].…”

mentioning

confidence: 99%

“…This paper is a journal expansion of the work reported in [15]. The main innovative contributions of this paper are as follows: 1) Incorporation of two independent bits in one PUF cell, including a thorough analysis of the mechanisms that enable this property and a Si implementation in 65nm.…”

mentioning

confidence: 99%

A 2 Bit/Cell Tilting SRAM-Based PUF With a BER of 3.1E-10 and an Energy of 21 FJ/Bit in 65nm

Shifman

Miller

Weizmann

et al. 2020

IEEE Open J. Circuits Syst.

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An SRAM-based Physical Unclonable Function (PUF) with two independent bits/cells is presented along with a tilting preselection test designed to identify all the unstable bits. Results of analysis of the Decision Voltage of the SRAM-based PUF cell indicate that in certain conditions, only the NMOS transistors in the cell impact its response, whereas the PMOS devices are in cutoff. Two pairs of NMOS transistors are inserted in the cell, each of which represents an orthogonal bit. The tilt test evaluates the internal mismatch within each of the NMOS pairs so that if it is insufficient, the resulting bit is considered unstable and masked from the PUF response. The cell demonstrated a highly competitive area of 1420F 2 per bit, a bit-error-rate (BER) of 3.1E-10, and a very low energy consumption of 21fJ/bit in 65nm. After preselection, the 2 bit/cell PUF exhibited a near-ideal inter-chip Hamming distance (49.5%) and percentage of ones (50.6%).

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An SRAM PUF with 2 Independent Bits/Cell in 65nm

Cited by 9 publications

References 6 publications

A Highly Reliable Reconfigurable SRAM PUF Based on Error Correction Codes and Capacitor Preselection

A Highly Reliable Reconfigurable SRAM PUF Based on Error Correction Codes and Capacitor Preselection

Hardware Security of Fog End-Devices for the Internet of Things

A 2 Bit/Cell Tilting SRAM-Based PUF With a BER of 3.1E-10 and an Energy of 21 FJ/Bit in 65nm

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