An SRAM weak cell fault model and a DFT technique with a programmable detection threshold

Pavlov, A.; Sachdev, Manoj; Gyvez, José Pineda de

doi:10.1109/test.2004.1387366

Cited by 15 publications

(18 citation statements)

References 13 publications

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“…Programmable stability fault detection has been described in [4,5,6]. These DfT techniques consist in using one or more core-cells per column to modulate the bit line voltage levels.…”

Section: B State-of-the-artmentioning

confidence: 99%

“…On the other hand, when the weak write stress is programmable, the test quality versus test yield tradeoff can be adjusted without design interactions and can be based only on the results of the post-silicon testing. Programmable threshold methods have been described in [4,5,6]. These DfT techniques consist in using the content of one or more core-cells in the column of the core-cell under test to modulate the bit line voltage levels and then use these levels to perform a weak write stress.…”

Section: Introductionmentioning

confidence: 99%

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A new design-for-test technique for SRAM core-cell stability faults

Ney¹,

Dilillo²,

Girard³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern in VDSM technologies. It provides information about the SRAM design reliability, and its effectiveness is therefore mandatory for safety applications. Existing core-cell stability Design-for-Test (DfT) techniques consist in controlling the voltage levels of bit lines to apply a weak write stress on the core-cell under test. If the core-cell is weak, the weak write stress induces the faulty swap of the core-cell. However, these solutions are costly in terms of area and test application time, and generally require modifications of critical parts of the SRAM (core-cell array and/or the structure generating the internal auto-timing). In this paper, we present a new DfT technique for stability fault detection. It consists in modulating the word line activation in order to perform an adjustable weak write stress on the targeted core-cell for stability fault detection. Compared to existing DfT solutions, the proposed technique offers many advantages: programmability, low area overhead, low test application time. Moreover, it does not require any modification of critical parts of the SRAM.

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“…Programmable stability fault detection has been described in [4,5,6]. These DfT techniques consist in using one or more core-cells per column to modulate the bit line voltage levels.…”

Section: B State-of-the-artmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A new design-for-test technique for SRAM core-cell stability faults

Ney¹,

Dilillo²,

Girard³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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show abstract

“…Reduction of R A B causes the gain reduction of the two inverters comprising an SRAM cell and proportionally reduces the cell's SNM. The WLPT is demonstrated to detect R A B <300kΩ (at V BL =0.55V) corresponding to the detected SNM degradation of 20% and more [2].…”

Section: -6-2mentioning

confidence: 98%

“…7(d)). R A B can be used as an SRAM cell stability fault model [2]. Reduction of R A B causes the gain reduction of the two inverters comprising an SRAM cell and proportionally reduces the cell's SNM.…”

Section: -6-2mentioning

confidence: 99%

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Programmable techniques for cell stability test and debug in embedded SRAMs

Pavlov

Sachdev

Gyvez³

et al.

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

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New SRAM design using body bias technique for low‐power and high‐speed applications

Faraji¹,

Naji²,

Rahimi-Nezhad³

et al. 2013

Circuit Theory & Apps

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In this paper, a new SRAM cell with body-bias actively controlled by a control circuit and word line is introduced to realize low-power and high-speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade-off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%.

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An SRAM weak cell fault model and a DFT technique with a programmable detection threshold

Cited by 15 publications

References 13 publications

A new design-for-test technique for SRAM core-cell stability faults

A new design-for-test technique for SRAM core-cell stability faults

Programmable techniques for cell stability test and debug in embedded SRAMs

New SRAM design using body bias technique for low‐power and high‐speed applications

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