An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning

Abstract

The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-m CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date.Index Terms-Analog-to-digital conversion, digital video broadcast-handheld (DVB-H), effective resolution bandwidth (ERBW), low-voltage circuits, pipeline analog-to-digital converter (ADC), power-efficient ADC.

Low power 9-bit pipelined A/D and 8-bit self-calibrated D/A converters for a DSP system

“…Figures of merit (FOM) and ENOB parameters of all ADC structures are also described. Table 1 shows that the FOM of the presented ADC is lower than that of the other ADC structures, except for the ADC [6]. The ENOB parameter of the presented ADC is comparable to that of the other ADC structures.…”

“…Figure 16 shows the FFT of the ADC output at 50Msamples/s with 24.95 MHz full-scale sine wave input above the Nyquist rate to avoid aliasing. The SFDR is 74.32 and SNDR is 51.83 dB K. Wawryn and R. Suszynski Table 1 and compared to the performances of known: switched capacitor (SC) voltage mode [5][6][7] and switched current (SI) [8,9] ADCs fabricated in the CMOS 0.35 µm and 0.25 µm technologies. Additionally, the performances of the pipelined ADCs fabricated in the CMOS 0.09 µm and 0.065 µm technologies [10][11][12][13] are shown in Table 1.…”

Generalized multiplying D/A converter stages for low-power pipelined A/D converters

“…On the other hand, although increasing f (f>1) makes the offset requirements of the comparators stringent, their number decreases. Therefore, with fractional gains the feedback factor of op-amps in MDACs can be relaxed with better gain distribution [3][4][5][6] at a slight penalty of increasing the power consumption of comparators. However, this is much less compared to power savings in op-amps.…”

“…The modeled op-amp is a single-stage gain boosted amplifier described in [2]. The developed system-level models are similar to [4] and [6] with extension to the general MDAC stages. The comparators in sub-A/D converters are selected as a dynamic latch with a pre-amplifier stage for highspeed and low kick-back noise.…”

“…In the literature already a set of general optimization methods are established and important observations regarding scaling of sampling capacitances and selection of bit-per-stage resolution of MDACs are reported [3][4][5][6]. However, all these strategies are evaluated on a sub-set of pipelined converters with MDAC gains of the form of 2 R .…”