An ultra-low-power extended counting ADC For large scale sensor arrays

Gao, Cencen; Wu, Dong; Liu, Hui; Xie, Ning; Pan, Liyang

doi:10.1109/iscas.2014.6865070

Cited by 7 publications

(6 citation statements)

References 7 publications

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“…The remaining time is used for the settling time. The SR is expressed by SR = ∆V T slewing (10) with ∆V the maximum output swing of the integrator and T slewing the chosen slewing time. The minimum SR calculated is 220 V/µs.…”

Section: Finite Gbw and Srmentioning

confidence: 99%

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A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor

Bisiaux

Lelandais-Perrault

Kolar

et al. 2016

2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)

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The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two-step design. A solution is to use the same hardware twice to perform both steps. This paper proposes a 14-b, 100 kHz Nyquist frequency, two-step incremental Σ∆ (IΣ∆) analogto-digital converter suitable for column-parallel CIS. Several architectures with different modulator order are compared to determine the most promising one. The proposed architecture, compared to a one-step second order modulator, reduces the total oversampling ratio (OSR) from 150 to 60 to reach a resolution of 14-b. The operational transconductance amplifiers (OTA) is the most critical part in our ADCs. Its required DCgain is around 80 dB for a 120 MHz gain-bandwidth product (GBW). The ideal DNL and INL of our two-step IΣ∆ ADC are respectively +0.55/-0.6 LSB and +0.5/-0.5 LSB. This work achieves a SNDR of 89 dB when a full scale sinusoid of 100 kHz is applied.

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Section: Finite Gbw and Srmentioning

confidence: 99%

“…In order to achieve a better tradeoff between speed and resolution, extended-counting ADCs (EC-ADC) have been reported [10] [11]. The EC-ADC is an hybrid architecture that performs the conversion in two steps.…”

Section: Introductionmentioning

confidence: 99%

A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor

Bisiaux

Lelandais-Perrault

Kolar

et al. 2016

2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI)

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“…The column-level extended-counting (E-C) ADC is one of the main schemes for uncooled infrared imagers [3,4,5]. Coarse A/D conversion is implemented by a feedback digital-to-analog converter (DAC) to fold the integrator's output during integration, thus to limit the output voltage to a low level.…”

Section: Introductionmentioning

confidence: 99%

“…This implementation is not only more suitable for low supply voltage, but also eases the noise requirement during fine A/D conversion. A capacitance-transimpedance-amplifier (CTIA) is often used as the integrator and is power-hungry to realize high slew-rate, high bandwidth and low distortion during folding integration [4]. In [4,5], a class-AB operational amplifier (op-amp) is used to satisfy the speed requirement.…”

Section: Introductionmentioning

confidence: 99%

“…A capacitance-transimpedance-amplifier (CTIA) is often used as the integrator and is power-hungry to realize high slew-rate, high bandwidth and low distortion during folding integration [4]. In [4,5], a class-AB operational amplifier (op-amp) is used to satisfy the speed requirement. Yet the input transistors' current becomes asymmetrical due to the variation of the output voltage and the output current.…”

Section: Introductionmentioning

confidence: 99%

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A Readout Circuit with Current-Compensation-Based Extended-Counting ADC for 1024×768 Diode Uncooled Infrared Imagers

Shi

Zhang

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a low-power readout circuit with 14-bit column-level extended-counting ADC for 17 -pitch × silicon diode uncooled infrared imagers. The ADC's coarse conversion adopts a current-mode DAC to feedback charge into a CTIA-based integrator during integration and the fine conversion is implemented by a SAR ADC after integration. A current self-compensator and a modified DAC are proposed to reduce more than 50% power of the overall integrator compared with conventional structure. The × readout circuit has been fabricated in the 0.18 1P5M CMOS process. Power consumption of the readout circuit is and each column ADC only consumes. Simulation results show that the RMS noise of the readout circuit is 0.9LSB and nonlinearity is 0.06% at 30fps.

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Neural Signal Quantization Circuits

Zjajo

2016

Brain-Machine Interface

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An ultra-low-power extended counting ADC For large scale sensor arrays

Cited by 7 publications

References 7 publications

A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor

A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor

A Readout Circuit with Current-Compensation-Based Extended-Counting ADC for 1024×768 Diode Uncooled Infrared Imagers

Neural Signal Quantization Circuits

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