An Ultra-Low-Power Programmable Analog Bionic Ear Processor

Sarpeshkar, Rahul; Salthouse, Christopher; Sit, Ji-Jon; Baker, Maureen; Zhak, S.M.; Lu, Timothy K.; Turicchia, L.; Balster, S.

doi:10.1109/tbme.2005.844043

Cited by 150 publications

(71 citation statements)

References 23 publications

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“…One aspect of this project that makes the feasibility a reality is that the current models of the ACC are control-loop or error driven based. This type of error-driven behavior has been previously demonstrated in neuromorphic models [17,18].…”

Section: Neuromorphic Model Of Accsupporting

confidence: 65%

“…In the past several years dedicated neuromorphic circuits have been constructed for various biological processes. Recent neuromorphic studies range from cochlear implantable processors [17], massive parallel networks of integrate and fire neurons [18], speech recognizers, sonar chips based on bat echolocation, and silicon retinas [19].…”

Section: B Neuromorphic Modelsmentioning

confidence: 99%

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Feasibility of neuro-morphic computing to emulate error-conflict based decision making.

Branch¹

2009

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A key aspect of decision making is determining when errors or conflicts exist in information and knowing whether to continue or terminate an action. Understanding the error-conflict processing is crucial in order to emulate higher brain functions in hardware and software systems. Specific brain regions, most notably the anterior cingulate cortex (ACC) are known to respond to the presence of conflicts in information by assigning a value to an action. Essentially, this conflict signal triggers strategic adjustments in cognitive control, which serve to prevent further conflict. The most probable mechanism is the ACC reports and discriminates different types of feedback, both positive and negative, that relate to different adaptations. Unique cells called spindle neurons that are primarily found in the ACC (layer Vb) are known to be responsible for cognitive dissonance (disambiguation between alternatives). Thus, the ACC through a specific set of cells likely plays a central role in the ability of humans to make difficult decisions and solve challenging problems in the midst of conflicting information. In addition to dealing with cognitive dissonance, decision making in high consequence scenarios also relies on the integration of multiple sets of information (sensory, reward, emotion, etc.). Thus, a second area of interest for this proposal lies in the corticostriatal networks that serve as an integration region for multiple cognitive inputs. In order to engineer neurological decision making processes in silicon devices, we will determine the key cells, inputs, and outputs of conflict/error detection in the ACC region. The second goal is understand in vitro models of corticostriatal networks and the impact of physical deficits on decision making, specifically in stressful scenarios with conflicting streams of data from multiple inputs. We will elucidate the mechanisms of cognitive data integration in order to implement a future corticostriatal-like network in silicon devices for improved decision processing.4

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Section: Neuromorphic Model Of Accsupporting

confidence: 65%

Section: B Neuromorphic Modelsmentioning

confidence: 99%

Feasibility of neuro-morphic computing to emulate error-conflict based decision making.

Branch¹

2009

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“…This requires amplifiers, ADCs, and DACs to be implemented in the latest CMOS process nodes to achieve high level of integration and low cost. Ultra low-power ADCs and analog blocks are also required in distributed wireless sensor networks [19], [2] and biomedical interface chips [20]. To achieve high power-efficiency while maintaining sufficient analog performance in terms of dynamic range, linearity etc., scaling-friendly ADC architectures such as the SAR ADC and the Σ∆ ADC are becoming increasingly popular.…”

Section: Low-power Adcs and Afesmentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

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In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...

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“…In addition, it was also possible to externally program its attack and release time constants so that it responded more quickly to increasing amplitudes than to decreasing ones. On the other hand, Sarpeshkar's final CI was also reported in 2005 (Sarpeshkar et al 2005). Their design achieved a total power consumption of 211µW (including microphone and stimulation circuits), a DR of 77dB and occupied an area of 9.58mm×9.23mm.…”

Section: And 2006mentioning

confidence: 99%