An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

Abdelfattah, Omar; Roberts, G.W.; Shih, I.; Shih, Yi-Chi

doi:10.1109/tcsi.2015.2469011

Cited by 101 publications

(43 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In recent years, a large number of LV BD OTAs have been reported in the literature. More specifically, new techniques for voltage gain boosting, 8,9,[11][12][13][14][15][16]20 increasing the input impedance, 5,10 reducing electromagnetic interference susceptibility 10,18 or transconductance variation with common-mode (CM) signal 17 were proposed. 6,16 Therefore, many papers are focused on overcoming the disadvantages of the BD technique rather than further decreasing the supply voltage.…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, a large number of LV BD OTAs have been reported in the literature. [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] Considering these designs, we can conclude that the supply voltage for many truly differential OTAs with a gain-bandwidth product (GBW) ranging from 1 to 10 MHz is nearly constant and equal to around |V TH | + 0.3 V. Lower V DD (close to |V TH |) could be achieved for circuits biased with very low currents (at the cost of a lower GBW), 7,14 or for circuits with pseudo-differential input stages. 6,16 Therefore, many papers are focused on overcoming the disadvantages of the BD technique rather than further decreasing the supply voltage.…”

Section: Introductionmentioning

confidence: 99%

“…[3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] Considering these designs, we can conclude that the supply voltage for many truly differential OTAs with a gain-bandwidth product (GBW) ranging from 1 to 10 MHz is nearly constant and equal to around |V TH | + 0.3 V. Lower V DD (close to |V TH |) could be achieved for circuits biased with very low currents (at the cost of a lower GBW), 7,14 or for circuits with pseudo-differential input stages. 6,16 Therefore, many papers are focused on overcoming the disadvantages of the BD technique rather than further decreasing the supply voltage. More specifically, new techniques for voltage gain boosting, 8,9,[11][12][13][14][15][16]20 increasing the input impedance, 5,10 reducing electromagnetic interference susceptibility 10,18 or transconductance variation with common-mode (CM) signal 17 were proposed.…”

Section: Introductionmentioning

confidence: 99%

“…6,16 Therefore, many papers are focused on overcoming the disadvantages of the BD technique rather than further decreasing the supply voltage. More specifically, new techniques for voltage gain boosting, 8,9,[11][12][13][14][15][16]20 increasing the input impedance, 5,10 reducing electromagnetic interference susceptibility 10,18 or transconductance variation with common-mode (CM) signal 17 were proposed.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Kulej

Khateb

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

A family of bulk-driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3-0.5 V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain-bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18-μm n-well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Kulej

Khateb

2018

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Source: author (KINGET; CHATTERJEE; TSIVIDIS, 2005). However, the bulk forward bias benefits and the improved input common-mode range have motivated the development of several bulk-driven operational amplifier circuits (CHATTERJEE; TSIVIDIS; KINGET, 2005a;TRAKIMAS;SONKUSALE, 2009;PAN et al, 2009;ABDELFATTAH et al, 2015;ZUO;ISLAM, 2013;KULEJ, 2013;FERREIRA et al, 2014;QIN et al, 2016).…”

Section: Gate and Bulk Input Amplifiersmentioning

confidence: 99%

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

Severo¹

View full text Add to dashboard Cite

I would like to thanks to Professor Wilhelmus Adrianus Maria Van Noije for the opportunity in work as a Ph.D. candidate at the Polytechnic School of the University of São Paulo and by all the challenges imposed to me that have collaborated significantly in the improvements of my professional abilities. I would like to thanks to the Federal University of Pampa for the opportunity of being on leave from the university by 3.5 years that made possible working full time in the Ph.D. studies and to the CNPq research agency for support to this work. I would also like to thanks to professors João A. Martino e Paula G. Der Agopian for all the help in the CMOS transistor characterization, to the IMEC Free-mini@asic and to the MOSIS Educational programs for the free integrated circuit fabrications and to professors João N. Soares Júnior and Márcio C. Schneider for all the suggestions gave me at the qualification exam. I would like to thanks to all the members of the DMPSV department of the LSI at USP, especially to Silvana, for all the conversations at the coffee time and commemoration during my stay in São Paulo. Finally, I thanks to my wife Tanísia for all the help and understanding during this shortage of time phase of my life.

show abstract

An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

Centurelli

Monsurrò

Scotti

et al. 2020

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed‐forward stage to obtain double pole‐zero cancellation and ideally single‐pole behavior, in a three‐stage Miller amplifier. The approach allows designing a three‐stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole‐zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity‐gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130‐nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single‐pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches.

show abstract

An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

Cited by 101 publications

References 18 publications

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

An improved reversed miller compensation technique for three‐stage CMOS OTAs with double pole‐zero cancellation and almost single‐pole frequency response

Contact Info

Product

Resources

About