An Ultra Low-Voltage RF Front-end Receiver for IoT Devices

Malena, Francesco; Aragones, X.; Mateo, D.; Caselli, Michele; Boni, Andrea

doi:10.1109/prime55000.2022.9816813

Cited by 2 publications

(3 citation statements)

References 11 publications

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“…The circuit in Fig. 6(b) is the row-interface for input activations, including a PWM DAC [16] and an analog multiplexer, based on the NMOS M B3 and the transmission gate T G B1 , converting the output signal of the DAC from logic levels to the 0-V B range. SOI devices, with 1.8-V nominal voltage supply (and 2-V strength) and compliant with the programming procedure in Fig.…”

Section: F-2t2r-based Memory Acceleratormentioning

confidence: 99%

“…4(b). A PWM-DAC, based on a digital delay line, with a resolution in the 5-to-7-bit range, can be laid out on two rows of digital standard cells [16]. In 22-nm FD-SOI, this approximately corresponds to a vertical array pitch H c = 1.2 µm.…”

Section: Accelerator Transistor-level Implementationmentioning

confidence: 99%

“…[20], [21], including only the consumption of the memory array and the interfaces, for a fair comparison. In our implementation, we consider the energy consumption of the DAC and of the ADC for mixed-signal accelerators, both in 22-nm, reported in [16] and [12]. An accelerator combining the F-2T2R cell with CMC type-2 is expected to achieve an energy efficiency, normalized to 1-b MAC, of 1260 1b-TOPS/W [22], at L r = 8, corresponding to 3.9-b weight resolution, and 7-b activations This value is approximately 10 times larger than the efficiency reported for the state-of-the art 1T1R accelerators [5], [7], [10].…”

Section: Accelerator Transistor-level Implementationmentioning

confidence: 99%

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Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications

Boni,

Malena,

Saccani

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This paper presents the Flipped (F)-2T2R RRAM compute cell enhancing the performance of RRAM-based mixedsignal accelerators for deep neural networks (DNNs) in machine learning (ML) applications. The F-2T2R cell is designed to exploit the features of the FD-SOI technology and it achieves a large increase in cell output impedance, compared to the standard 1T1R cell. The paper also describes the modelling of an F-2T2Rbased accelerator and its transistor-level implementation in a 22nm FD-SOI technology. The modelling results and the accelerator performance are validated by simulation. The proposed design can achieve an energy efficiency of up to 1260 1b-TOPS/W, with a memory array of 256 rows and columns. From the results of our analytical framework, a ResNet18, mapped on the accelerator, can obtain an accuracy reduction below 2%, with respect to the floating point baseline, on the CIFAR-10 dataset.

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Section: F-2t2r-based Memory Acceleratormentioning

confidence: 99%

Section: Accelerator Transistor-level Implementationmentioning

confidence: 99%