An unconstrained relaxation digital‐to‐analog converter using optimal bit sequence

Abstract

Based on the relaxation digital‐to‐analog converter (ReDAC) architecture and the capacitor charge/discharge function under discrete time conditions, this paper proposes a new mathematical model for the output voltage of the ReDAC to implement the unconstrained relaxation DAC (Uc‐ReDAC). The system clock calibration is not required. An adaptive probabilistic binary particle swarm optimization (AP‐BPSO) algorithm is proposed for solving the binary coding configuration problem under the Uc‐ReDAC model. Simulation results show that the 8‐bit (10‐bit) Uc‐ReDAC has an average sampling rate of 7.9 MS/s (6.76 MS/s).