Analog AGC Circuitry for a CMOS WLAN Receiver

Jeon, O.; Fox, R.M.; Myers, B.A.

doi:10.1109/jssc.2006.881548

Cited by 114 publications

(35 citation statements)

References 6 publications

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“…7(a), the traditional analog AGC loop is composed of analog VGA, ADC and charge pump [13,17]. It is difficult to automatically and accurately adjust the parameters of D and R according to the power strength of Gaussian noise or jamming because of the unmatched charge currents; furthermore the external capacitor make AGC loop can not be fully integrated [8,17].…”

Section: Compared With Analog Agcmentioning

confidence: 99%

A tri-mode Compass/GPS/Galileo RF receiver with all-digital automatic gain control loop

Chen

Yan

Jin

et al. 2011

Analog Integr Circ Sig Process

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A tri-mode RF receiver with all digital automatic gain control (AGC) loop and non-uniform 2-bit analog-to-digital converter (ADC) is designed for the bands of GPS-L1, Galileo-E1 and Compass B1 in 0.18 lm CMOS process. The RF front-end, analog baseband and frequency synthesizer with voltage controlled oscillator (VCO) have been integrated, and there are only few offchip components including bypass capacitances, matching network and TCXO. For anti-jamming consideration, an all digital AGC loop with relevant variable gain amplifier (VGA) and non-uniform ADC is implemented to suppress interference and avoid saturation of signal chain. While drawing 35 mA current, this receiver achieves a total noise figure of 4 dB and a maximum gain of 105 dB, with a die area of 2.4 9 2.4 mm 2 .

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Section: Compared With Analog Agcmentioning

confidence: 99%

A tri-mode Compass/GPS/Galileo RF receiver with all-digital automatic gain control loop

Chen

Yan

Jin

et al. 2011

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…But, it suffers from a small amplitude margin due to lanedependent signal attenuation and from a small timing margin due to timing skew caused by gain mismatch among lanes, which indicates that a highly accurate gain calibration is required. To address the issue, analog gain mismatch calibration loops were proposed [2,3]. But, they are not adequate for multi-lane applications because the loop should be implemented separately for each lane, resulting in substantial increase on power consumption and area as the number of lane increases.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

Lim¹,

Kong²,

Jun³

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a SD ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at 10 -6 BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

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“…The linearity and good noise performance of PGAs are proven in CMOS Processes. However, continuous gain control is mandatory in some applications such as orthogonal frequency-division multiplexing (OFDM), wideband code-division multiple access (WCDMA) or impulse radios [2,[9][10][11][12][13]. The constantbandwidth and linear-in-dB gain control characteristics are two important features of VGA that must be satisfied in order to preserve the constant settling time and delay group of AGC loop [14].…”

Section: Introductionmentioning

confidence: 99%

A 0.74 mW, linear-in-dB, constant bandwidth, variable gain amplifier based on zero-pole repositioning technique

Baghtash

2015

Analog Integr Circ Sig Process

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A zero-pole repositioning based variable gain amplifier is presented in this paper. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by simulation in TSMC 0.18 lm standard CMOS technology. Owing to the cutting-edge structure, the proposed circuit demonstrates a very low power consumption of 0.74 mW and a wide tuning range of 83 dB. The proposed structure benefits from linear-in-dB and constant bandwidth specifications. The linear-in-dB gain range of structure is about 70 dB. The structure draws about 413 lA from 1.8 V power supply and regarding this low power consumption, it shows a lower and upper 3-dB cutoff frequencies of 8 Hz and 8.1 MHz, respectively. Process and temperature variation analysis of the circuit is also investigated through Monte Carlo and corner case analysis in order to verify the well-robustness of the structure. The transient sinusoidal response analysis is also done to verify the proposed VGA's stability.

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Analog AGC Circuitry for a CMOS WLAN Receiver

Cited by 114 publications

References 6 publications

A tri-mode Compass/GPS/Galileo RF receiver with all-digital automatic gain control loop

A tri-mode Compass/GPS/Galileo RF receiver with all-digital automatic gain control loop

Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

A 0.74 mW, linear-in-dB, constant bandwidth, variable gain amplifier based on zero-pole repositioning technique

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