Analog Circuits Sizing Using Multi-Objective Evolutionary Algorithm Based on Decomposition

Abstract

Several analog circuit design has been suggested where a layout generator is used after a circuit sizing. But, many iterations between circuit sizing and layout generator stages are needed to obtain desired specifications. This paper proposes a new equation and simulation-based method for circuits sizing of CMOS operational amplifiers (op-amps) by considering layout effects. In the proposed method, layout effects are considered during the sizing step. Layout effects are devices parasitics and geometry information that are extracted from a new automated layout generator. Optimization is performed using multi-objective evolutionary algorithm based on decomposition (MOEA/D). In order to evaluate the performance of the proposed sizing method, the design of foldedcascode and three-stage op-amps are provided in a 0.18µm process CMOS technology with 1.8 V supply voltage. The simulation results exhibit the good performance of the proposed sizing method.