Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

Alimisis, Vassilis; Gourdouparis, Marios; Gennis, Georgios; Dimas, Christos; Sotiriadis, Paul P.

doi:10.3390/electronics10202530

Cited by 19 publications

(8 citation statements)

References 93 publications

(284 reference statements)

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“…The volume of input dimensions is contingent on the multidimensional Gaussian function circuit. While there exist various circuits that yield PDFs, extant literature confines their application to dimensions of a modest scale, typically less than 16 [20,65].…”

Section: Proposed Design Methodologymentioning

confidence: 99%

“…A broad spectrum of bump circuits has been developed for numerous applications [20]. However, for the purposes of this research, a modified version of the bump circuit (aspect ratio equal to 7) [65], as shown in Figure 3, has been employed to enhance the quality and resilience of the resulting Gaussian curve.…”

Section: Gaussian Function Circuitmentioning

confidence: 99%

“…It is realized based on a Bayesian mathematical model [19] using two main sub-circuits. Specifically, the employed main building blocks are ultra-low-power Gaussian function circuits [20] and an argmax operator circuit [21]. Post-layout simulation results are conducted on a TSMC 90 nm CMOS process using the Cadence IC suite and compared with a software-based implementation.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

Alimisis,

Eleftheriou,

Kamperi

et al. 2023

Electronics

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This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity.

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Section: Proposed Design Methodologymentioning

confidence: 99%

Section: Gaussian Function Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

Alimisis,

Eleftheriou,

Kamperi

et al. 2023

Electronics

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“…Architectures tailored specifically to ML algorithms and models in an analog hardware implementation leverage circuits grounded in Gaussian functions [38]. A subsection consolidates the distinctive features of system-level implementations integrated with Gaussian function circuitry.…”

Section: Background 21 Related Literaturementioning

confidence: 99%

A Low-Power Analog Integrated Euclidean Distance Radial Basis Function Classifier

Alimisis,

Dimas,

Sotiriadis

2024

Electronics

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This study introduces a low-power analog integrated Euclidean distance radial basis function classifier. The high-level architecture is composed of several Manhattan distance circuits in connection with a current comparator circuit. Notably, each implementation was designed with modularity and scalability in mind, effectively accommodating variations in the classification parameters. The proposed classifier’s operational principles are meticulously detailed, tailored for low-power, low-voltage, and fully tunable implementations, specifically targeting biomedical applications. This design methodology materialized within a 90 nm CMOS process, utilizing the Cadence IC Suite for the comprehensive management of both the schematic and layout design aspects. During the verification phase, post-layout simulation results were meticulously cross-referenced with software-based classifier implementations. Also, a comparison study with related analog classifiers is provided. Through the simulation results and comparative study, the design architecture’s accuracy and sensitivity were effectively validated and confirmed.

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“…Pursuing a probabilistic inference, significant strides have been made in recent years to develop devices capable of physically emulating the characteristics of a Gaussian function 30 – 33 . This physics-based computing approach, using the Gaussian devices, holds the potential for a revolutionary enhancement in energy efficiency, thereby enabling efficient operation of GMMs with highly constrained resources.…”

Section: Introductionmentioning

confidence: 99%

Highly parallel and ultra-low-power probabilistic reasoning with programmable gaussian-like memory transistors

Lee,

Rahimifard,

Choi

et al. 2024

Nat Commun

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Probabilistic inference in data-driven models is promising for predicting outputs and associated confidence levels, alleviating risks arising from overconfidence. However, implementing complex computations with minimal devices still remains challenging. Here, utilizing a heterojunction of p- and n-type semiconductors coupled with separate floating-gate configuration, a Gaussian-like memory transistor is proposed, where a programmable Gaussian-like current-voltage response is achieved within a single device. A separate floating-gate structure allows for exquisite control of the Gaussian-like current output to a significant extent through simple programming, with an over 10000 s retention performance and mechanical flexibility. This enables physical evaluation of complex distribution functions with the simplified circuit design and higher parallelism. Successful implementation for localization and obstacle avoidance tasks is demonstrated using Gaussian-like curves produced from Gaussian-like memory transistor. With its ultralow-power consumption, simplified design, and programmable Gaussian-like outputs, our 3-terminal Gaussian-like memory transistor holds potential as a hardware platform for probabilistic inference computing.

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Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

Cited by 19 publications

References 93 publications

General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

A Low-Power Analog Integrated Euclidean Distance Radial Basis Function Classifier

Highly parallel and ultra-low-power probabilistic reasoning with programmable gaussian-like memory transistors

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