Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

Wang, Runsheng; Zhuge, Jing; Huang, Ru; Tian, Yu; Xiao, Han; Zhang, Liangliang; Li, Chen; Zhang, Xing; Wang, Yangyuan

doi:10.1109/ted.2007.896598

Cited by 90 publications

(15 citation statements)

References 22 publications

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“…The results obtained here are similar to the data calculated in Ref. 8. The cut-off frequency increases as the nanowire diameter decreases.…”

supporting

confidence: 91%

“…For that purpose, a three dimensional full-band quantum transport simulator based on the sp 3 d 5 s * tight-binding (TB) model 12,13 is used. As the maximum oscillation frequency (f max )another important figure of merit of the RF MOSFETs is directly related to the cut-off frequency 8 , the effects of IRS on the theoretical limit of the SiNWT's RF performance can be estimated through this study.…”

mentioning

confidence: 99%

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Effects of interface roughness scattering on radio frequency performance of silicon nanowire transistors

Kim

Luisier

Boykin

et al. 2011

Applied Physics Letters

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The effects of an atomistic interface roughness in n-type silicon nanowire transistors (SiNWT) on the radio frequency performance are analyzed. Interface roughness scattering (IRS) is statistically investigated through a three dimensional full-band quantum transport simulation based on the sp 3 d 5 s * tight-binding model. As the diameter of the SiNWT is scaled down below 3 nm, IRS causes a significant reduction of the cut-off frequency. The fluctuations of the conduction band edge due to the rough surface lead to a reflection of electrons through mode-mismatch. This effect reduces the velocity of electrons and hence the transconductance considerably causing a cut-off frequency reduction.Keywords: interface roughness scattering, silicon nanowire transistor, RF, cut-off frequency Since the lengths of silicon (Si) metal-oxidesemiconductor field effect transistor (MOSFET) have been scaled down to the sub-100 nm regime, the cutoff frequency has increased significantly to reach hundreds of gigahertz (GHz) 1-3 . Even though the cut-off frequency is not the only important parameter in radio frequency (RF) MOSFETs, a high cut-off frequency certainly represents a good criterion for Si MOSFETs to catch up with III-V transistors if other shortcomings are overcome. Power losses due to a long skin depth of the Si substrate, a poor noise figure and a high gate resistance 4 are the examples of such obstacles. Recently there have been tremendous efforts to improve the RF performance of the Si MOSFET and it is becoming competitive to III-V high electron mobility transistor (HEMT)/heterojunction bipolar transistor (HBT) or silicon germanium (SiGe) HBT 2,3,5 . Silicon-on-insulator (SOI) multi-gate (MG) structures also have been found to be capable of achieving the cutoff frequency predicted by the international technology roadmap for semiconductors (ITRS) 6 for RF applications while reducing substrate losses and noise figures 7 . Gateall-around (GAA) siicon nanowire transistors (SiNWTs) have attracted attention since it was found that their cutoff frequency can be much larger than that of planar Si MOSFET 8 . Traditionally, interface roughness scattering (IRS) has been considered as one of the most important scattering mechanisms. At a high effective electric field, IRS dominates the universal mobility trend 10 . In SiNWTs, IRS is still an important scattering mechanism reducing the oncurrent and the mobility significantly from the ballistic values 11 .a) Electronic mail: kim568@purdue.edu.This paper focuses on the effects of interface roughness scattering on the RF performance of SiNWTs, especially on the cut-off frequency (f T ). For that purpose, a three dimensional full-band quantum transport simulator based on the spis used. As the maximum oscillation frequency (f max ) -another important figure of merit of the RF MOSFETs is directly related to the cut-off frequency 8 , the effects of IRS on the theoretical limit of the SiNWT's RF performance can be estimated through this study.The structure of the SiNWT studied in this pap...

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“…The results obtained here are similar to the data calculated in Ref. 8. The cut-off frequency increases as the nanowire diameter decreases.…”

supporting

confidence: 91%

mentioning

confidence: 99%

Effects of interface roughness scattering on radio frequency performance of silicon nanowire transistors

Kim

Luisier

Boykin

et al. 2011

Applied Physics Letters

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show abstract

“…Table 2 lists the several structural parameters and Table 3 summarizes the various physical models employed during the simulation process using the ATLAS 3-D simulator. 2 Also, the channel region of our device has been splitted into three sections, i.e. : Section I: 0 ⩽ x ⩽ t si ; 0 ⩽ y ⩽ L 1 : Section II: 0…”

Section: Device Descriptionmentioning

confidence: 99%

“…Nowadays, the dimensions of the MOSFET are getting shrinked which brings about a trouble called as short-channel effects (SCEs). 1,2 Therefore, in order to tackle with these SCEs, numerous multi-gate (Double gate, Fin-FETs, Surrounding Gate) MOSFETs, [3][4][5][6] silicon-on selective-buried oxide (SELBOX) MOSFETs 7 were introduced and found to be more superior compared to the conventional MOSFETs. These topologies offer lesser SCEs and thus, improved characteristics.…”

Section: Introductionmentioning

confidence: 99%

Analytical model for junctionless accumulation‐mode cylindrical surrounding gate (JAM‐CSG) MOSFET as a biosensor

Gupta

Pandey

Gupta

2023

Int J Numerical Modelling

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This article proposes analytical modeling for Junctionless Accumulation‐Mode Cylindrical Surrounding Gate (JAM‐ CSG) MOSFET‐based biosensor used for label free electrical detection of the biomolecules (enzymes, cells, DNA, etc.). Modeling has been performed using the Poisson's equation and considering parabolic potential profile. A nanogap cavity is being created for providing a binding site for the biomolecules. Influence of both the neutral and charged biomolecules immobilized in the nanogap cavity has been studied. The change in the threshold voltage is being utilized as a measure for detecting the existence of the biomolecules inside the cavity region. The sensitivity parameter has also been found considering different cavity heights. ATLAS device simulator has been utilized for conducting the simulations. Furthermore, the analytical model outcomes are validated with the simulated ones. Results acquired verify the considered device to be able to work as a highly sensitive biosensor.

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“…They inherently offer good suppression of short-channel effects (SCEs), have high transconductance (g m ) and exhibit ideal subthreshold swing (S.S.). Among the aforementioned multiple-gate devices, the round-shaped surrounding-gate MOSFET is the structure for use in nextgeneration high-performance nano-devices as well as in analog and digital circuits [12][13][14][15][16][17][18]. As well as offering perfect channel controllability because of the complete 100% gate coverage, the surrounding-gate MOSFET tolerates a thicker silicon fin than with double-and triple-gate devices [19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

Hwang

2009

Semicond. Sci. Technol.

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The silicon (Si) surrounding-gate metal-oxide-semiconductor field-effect transistor (MOSFET) has ultimate gate structures and is a potential candidate for use in next-generation high-performance nano-devices. However, because of limitations of the fabrication process, theoretically ideally round shape of the surrounding gate may not always guarantee. These limitations may lead to the formation of an ellipse-shaped surrounding gate with major (a) and minor (b) axes of different lengths. In this study, the effect of the geometry aspect ratio, a/b, on the dc and ac characteristics of the 16 nm gate ellipse-shaped surrounding-gate MOSFETs and circuits is examined by using a three-dimensional coupled device-circuit simulation technique. The dependences of electrical characteristics on the geometry aspect ratio are evaluated with reference to various device characteristics and the circuit properties, including the circuit gain, the 3 dB bandwidth, the unity-gain bandwidth, the rise/fall time and the delay time. In analog circuits, the device with an aspect ratio of less than 1 is promising because the short-channel effect is suppressed. However, for a digital circuit configuration, the transient response of the circuit relies on the charge/discharge capability of the transistor. Thus, a device with a large aspect ratio, such as 2, will be more suitable for digital applications.

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Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

Cited by 90 publications

References 22 publications

Effects of interface roughness scattering on radio frequency performance of silicon nanowire transistors

Effects of interface roughness scattering on radio frequency performance of silicon nanowire transistors

Analytical model for junctionless accumulation‐mode cylindrical surrounding gate (JAM‐CSG) MOSFET as a biosensor

The effect of the geometry aspect ratio on the silicon ellipse-shaped surrounding- gate field-effect transistor and circuit

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