Analog Spiking Neuron in 28 nm CMOS

Abstract

The computational complexity of deep learning algorithms has given rise to significant speed and memory challenges for the execution hardware. In energy-limited portable devices, highly efficient processing platforms are indispensable for reproducing the prowess afforded by much bulkier processing platforms.In this work, we present a low-power Leaky Integrate-and-Fire (LIF) neuron design fabricated in TSMC's 28 nm CMOS technology as proof of concept to build an energy-efficient mixed-signal Neuromorphic System-on-Chip (NeuroSoC). The fabricated neuron consumes 1.61 fJ/spike and occupies an active area of 34 µm 2 , leading to a maximum spiking frequency of 300 kHz at 250 mV power supply.These performances are used in a software model to emulate the dynamics of a Spiking Neural Network (SNN). Employing supervised backpropagation and a surrogate gradient technique, the resulting accuracy on the MNIST dataset, using 4-bit posttraining quantization stands at 82.5%. The approach underscores the potential of such ASIC implementation of quantized SNNs to deliver high-performance, energy-efficient solutions to various embedded machine-learning applications.

A CMOS LIF neuron based on a charge-powered oscillator with time-domain threshold logic

“…The simulation results show a promising <40fJ/spike initial proof-of-concept. In addition, refinements in this time-based LIF architecture, such as implementation in lower lithography nodes, may bring the proposed architecture closer to some of the best power-efficient neurons currently researched [10].…”

Jitter Noise Impact on Analog Spiking Neural Networks: STDP Limitations

“…This eNeuron achieves an E e f f of 2 fJ/spike but with a low f spike of 15 kHz. Besrour et al have designed a LIF eNeuron (eNeuron4) [11]. This eNeuron consists of 6 transistors and two capacitors.…”

“…In this case, S I n refers to the shot noise, modeled as S I n = 2 q I D . Z out ( f ) is the output impedance of the eNeuron circuit and is formed by [10], and eNeuron4 using 6.5 × 7.8 µm 2 [11].…”

“…Additionally, its order of magnitude is estimated to evaluate if the temporal learning rules can be used in analog SNNs. Previously published eNeurons from [3], [9]- [11] using BiCMOS 55 nm technology and a temporal learning rule as STDP are described in Sec.II. Section III proposes the noise analytical tools.…”

“…Fig.5. Proposed layouts for eNeurons under test: (a) eNeuron1 using 5.7 × 17.3 µm 2[3], (b) eNeuron2 using 2.3 × 2.7 µm 2 [9], eNeuron3 using 6.6 × 4.3 µm 2[10], and eNeuron4 using 6.5 × 7.8 µm 2[11].…”