Analog Versus Digital Control of a Clock Synchronizer for 3 gb/s Data with 3.ov Differential Ecl

Izzard, Martin; Thisell, C.G.; Mader, Hermann; Hedberg, M.; Fung, P.K.; Chang, Hsiu-Ju; Larsson, B.; Venugopal, Gunasekaran; Scott, David B.

doi:10.1109/vlsic.1994.586201

Cited by 1 publication

(2 citation statements)

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“…A compromising solution is to extend the VCDL range and use an FSM that controls the loop start-up. However, DLL's relying on quadrature phase mixing [2], [3] completely eliminate this problem. This approach is based on the fact that quadrature clocks can be easily generated, given a clock of the correct frequency.…”

Section: A Conventional Dll'smentioning

confidence: 99%

“…More interesting is the transfer function of the input clock to dual-loop error since changes in the period of the input clock will cause both the core and peripheral loop to react. Based on (1) and 2, this transfer function can be shown to be (3) This bandpass transfer function exhibits no peaking at any frequency regardless of the relative magnitudes of and . The step response of the system, shown in Fig.…”

Section: Dual-loop Dynamicsmentioning

confidence: 99%

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A semidigital dual delay-locked loop

Sidiropoulos

Horowitz

1997

IEEE J. Solid-State Circuits

302

113

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This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-m CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peakto-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV.

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Section: A Conventional Dll'smentioning

confidence: 99%

Section: Dual-loop Dynamicsmentioning

confidence: 99%