Analogue signal and image processing with large memristor crossbars

Li, Can; Hu, Miao; Li, Yuning; Jiang, Hao; Ge, Ning; Montgomery, Eric; Zhang, Jiaming; Song, Wenhao; Dávila, Noraica; Graves, Catherine E.; Li, Zhiyong; Strachan, John Paul; Lin, Peng; Wang, Zhongrui; Barnell, Mark; Wu, Qing; Williams, R. Stanley; Yang, J. Joshua; Xia, Qiangfei

doi:10.1038/s41928-017-0002-z

Cited by 1,037 publications

(806 citation statements)

References 39 publications

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“…Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy. [12,16,25] This brings another challenge: compatibility of memristor and CMOS. [6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes.…”

mentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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in computing accelerators compared to high density storage-class memory, it is frequently important in computing applications to program multiple bits of information within every device by achieving many distinct conductance levels, while keeping the operating currents lower especially at the high conductance states. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy. For example, in analog matrix-vector multiplication, voltage drops across metal interconnect lines cause computational errors and, therefore, the memristor array size must be limited. [6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. This further benefits the energy and area efficiency by amortizing the costs of anolog to digital converters (ADC) required in the circuit. [4] However, existing demonstrations have a narrow dynamic range and achieving multiple low conductance levels is challenging. A larger ratio between the high and low conductances (on/off ratio) helps in achieving more distinct programmable low conductance levels. In addition, memristors are required to be integrated with CMOS circuits in many such applications. For instance, a 1-transistor-1-memristor (1T1M) combination provides in situ current compliance through gate voltage modulation so that the memristor can be programmed in an analog manner. [12,16,25] This brings another challenge: compatibility of memristor and CMOS. This includes not only material and fabrication compatibility, but also CMOS performance meeting the memristor operating requirements as both continue size scaling. Thus, it is essential to demonstrate all the aforementioned properties in nanometer-scale memristors repeatedly and reproducibly.Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.Using memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. Such accelerators have demonstrated the potential to significantly outperform digital computers in highly relevant applications such as machine learning and image processing. However, improvements in device-level performance of memristors, including reducing power consumption and high current-induced metal migration in interconnects, need continued developments. Nanoscaling and complementary metal-oxide semiconductor (CMOS) integration are also of significant ...

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mentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

Self Cite

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“…[13,77,78] The edge computing could alleviate burdens of data transmission between edge devices and large data center and accelerate data processing in large data centers. [13,14] Nevertheless, the challenges in power con-sumption, device reliability, and high-density integration hinder the development of TMOs based memristive devices. [13,14] Nevertheless, the challenges in power con-sumption, device reliability, and high-density integration hinder the development of TMOs based memristive devices.…”

Section: Memristive Devicesmentioning

confidence: 99%

“…These features make them ideal candidates for applications in memory devices, [3,5,9] in-memory computing, [3,[10][11][12] and edge computing. [13,14] The working principle of the TMOs-based memristive devices relies on ion drift or diffusion, which resembles motion of ions in the biological neurons and synapses. The ionic motions exhibit dynamic behaviors.…”

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confidence: 99%

2D Layered Materials for Memristive and Neuromorphic Applications

Wang

Meng

et al. 2019

Adv Elect Materials

101

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demonstrated that the memristive devices exhibit many promising features, [3][4][5][6][7][8] such as non-volatility, high speed switching, high endurance, high-density integration, CMOS-compatible fabrication, and so on. These features make them ideal candidates for applications in memory devices, [3,5,9] in-memory computing, [3,[10][11][12] and edge computing. [13,14] The working principle of the TMOs-based memristive devices relies on ion drift or diffusion, which resembles motion of ions in the biological neurons and synapses. The ionic motions exhibit dynamic behaviors. Thus, the memristive devices can be used to emulate the synaptic plasticity [15] and neurons. [16][17][18] Compared to traditional silicon synapses [19][20][21] and neurons [22,23] requiring complex circuits, such emerging memristive devices have compact structures and enhanced func-

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“…The shape extraction process is illustrated in Fig. 4 (b)(the image used for processing comes from 29 ). With artificial shape perception retina network, the grayscale matrix is transformed into the frequency matrix, and the edges in the image were detected.…”

Section: Introductionmentioning

confidence: 99%

Artificial Shape Perception Retina Network Based on Tunable Memristive Neurons

Bao

Kang

Fang

et al. 2018

Sci Rep

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Retina shows an extremely high signal processing efficiency because of its specific signal processing strategy which called computing in sensor. In retina, photoreceptor cells encode light signals into spikes and ganglion cells finish the shape perception process. In order to realize the neuromorphic vision sensor, the one-transistor-one-memristor (1T1M) structure which formed by one memristor and one MOSFET in serial is used to construct photoreceptor cell and ganglion cell. The voltage changes between two terminals of memristor and MOSFET can mimic the changes of membrane potential caused by spikes and illumination respectively. In this paper, the tunable memristive neurons with 1T1M structures are built. According to the concept of receptive field of ganglion cells (GCs) in the retina, the artificial shape perception retina network is constructed with these memristive neurons. The final results show that the artificial retina can extract shape information from the image and transfer it into spike frequency realizing the function of computing in sensor.

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Analogue signal and image processing with large memristor crossbars

Cited by 1,037 publications

References 39 publications

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

2D Layered Materials for Memristive and Neuromorphic Applications

Artificial Shape Perception Retina Network Based on Tunable Memristive Neurons

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