Analysis and acceleration of data mining algorithms on high performance reconfigurable computing platforms

Sun, Shuli

doi:10.31274/etd-180810-795

Cited by 10 publications

(2 citation statements)

References 135 publications

(214 reference statements)

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“…Therefore, the most frequent item appears four times (the computed Hamming weight plus 1) in the original set and this is item 21 (the item whose index is 7 in the sorted set). Other practical applications are described in [16][17][18][19][20][21][22][23][24]. Since many systems have hard real-time constraints, performance is important and hardware accelerators may provide significant assistance.…”

Section: Introductionmentioning

confidence: 99%

Hardware accelerators for processing clusters in binary vectors

Skliarova,

Skliarov

2024

ITM Web Conf.

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The paper suggests fast hardware accelerators for discovering clusters of zeros and/or ones in binary vectors. Any cluster is composed of successive bits with the same value (either 1 or 0). Search for such segments is required in many practical problems, for example, coding, data, and image processing. The proposed solutions enable, for a given vector, answering such questions as how many one/zero clusters can be found; what is the largest number of consecutive ones/zeros; what is the number of clusters having k consecutive ones/zeros; is the vector only composed of segments with exactly k consecutive ones/zeros; and some others. The relevant practical applications, for which acceleration is required, are also discussed. The paper suggests two core architectural solutions that are based on combinational and iterative networks of gates. Each network is modeled in software (C++ language) and then specified in a hardware-description language (VHDL), synthesized, and implemented in FPGA. Finally, the results of the circuits’ evaluations and comparisons are presented.

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Section: Introductionmentioning

confidence: 99%

Hardware accelerators for processing clusters in binary vectors

Skliarova,

Skliarov

2024

ITM Web Conf.

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“…accelerated and may be used in many known methods from this scope, e.g. [2]- [4]. Another example can be taken from the area of control.…”

Section: Introductionmentioning

confidence: 99%

Processing Sorted Subsets in a Multi-level Reconfigurable Computing System

Rjabov

Sklyarov

Skliarova

et al. 2015

ElAEE

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The paper suggests a technique for extracting and filtering sorted subsets in a three-level computing system with such sub-systems as general-purpose computer (level 1), ARM Cortex-A9 (level 2), and reconfigurable logic (level 3). The last two levels are implemented in Zynq-7000 device available on the prototyping board ZC706. Communications between the levels 1 and 2-3 are organized through PCI express bus and interactions between components of levels 2 and 3through on-chip AXI interfaces. We studied two levels of software programs (running in PC and ARM), highperformance hardware accelerators implemented in Zynq-7000 programmable logic, and architecture enabling interactions and exchange of data between different levels. The selected for analysis sorting problem has high computational complexity and is widely required in data processing (data mining and statistical data manipulation, in particular). The results of experiments demonstrate that the elaborated architecture is efficient and permits fast solutions to be found. Proposals for potential further improvements are also given.

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