Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Random discrete dopant induced variability in negative capacitance transistors

“…We use the 3-D device simulator GARAND [7] to obtain the charge-voltge and current-voltage characteristics of the reference MOS transistor. We then calculate the potential drop across the ferroelectric using the steady-state Landau-Khalatnikov equation [8], [9]. Finally we map the internal gate bias to the actual (external) gate bias using voltage balance, thus obtaining the terminal characteristics of the NCFET.…”

“…The operation of NCFETs based on capacitance matching, their typical characteristics and dependence on ferroelectric thickness and matarial parameters have been described elsewhere (e.g. see [8], [9], [11], [12]) and will not be discussed here. Also, note that the variability in the ferroelectric layer itself is not considered here, as the focus is to isolate the impact of the NC effect on RDD induced variability.…”

A Thermodynamic Perspective of Negative-Capacitance Field-Effect Transistors

“…As a result, it is of importance to have a clear picture for the underlying physics behind FeFETs for both memory and logic operation regimes. Unlike previous works focusing solely on the particular application: (i.e., presuming that initially FeFETs are in the NC regions [6], [13], [14], [15] or a clear hysteresis loops are established in FE oxides [16]), this paper does not assume any particular operation region initially and provides a unified picture of how FeFET operation transitions from memory to logic devices due to the change of thermodynamic free energy profiles. This picture is verified by numerical simulations incorporating MOS electrostatics and polarization dynamics self-consistently.…”

Modeling emerging technologies using machine learning

“…BSIM-CMG [1] is used for conventional FinFET. A compact model [6] based on BSIM-CMG is used for emerging NC-FinFET. Details on the used NC-FinFET modeling and FinFET device calibration with industrial measurements are available in [20] and [21], respectively.…”

“…To provide a proof of concept, our NN-based transistor model is calibrated to a commercial 14 nm FinFET technology [5], as well as NC-FinFET [6] as our example of an emerging technology. The transistor model is able to match NC-FinFET just as well as conventional FinFET despite the material and structural innovations in NC-FinFET (ferroelectric gates, which acts as a negative capacitance providing voltage amplification and negative drain induced barrier lowering).…”