Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems

Abstract

Abstract-In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the energy dissipation in the tree. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower energy in subthreshold circuits.Index Terms-Design automation, reliability, system analysis and design.

Design Methodology for Voltage-Scaled Clock Distribution Networks

“…This approach has been extended to clock networks due to high clock net capacitance [8]- [11]. Clock networks operating at near-threshold voltages have also been investigated [12]- [14].…”

“…Automated CTS algorithms were not considered. Tolbert et al [12] and Zhao et al [14] proposed a deferred merge embedding (DME)-based CTS method for low-voltage clock networks with an emphasis on clock slew. The proposed technique relies on a computationally expensive procedure of storing multiple solutions in a bottom-up fashion, followed by selecting an optimum solution for each node in a top-down fashion.…”