Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

Abstract

The embedded Flash (eFlash) technology can be subject to defects creating functional faults. In this paper, we first generalize the electrical model of the ATMEL TSTAC™ eFlash memory technology proposed in [10]. The model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model is validated by means of simulations and comparisons with ATMEL silicon data. Then, we present a complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC™ eFlash array by considering the proposed model on a hypothetical 4×4 array. This analysis highlights the interest of the proposed model to provide a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. Responsible Editor: C. A. Papachristou This paper is an extended version of a previously published paper. Main contributions of this paper with respect to [10] are: -A generalization of the model initially proposed in [10] to the case of multiple word-lines, -A complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC/ eFlash array, -A fault modeling of actual resistive defect injection.