Analysis and implementation of parallel causal bit plane coding in JPEG2000 standard

Ghodhbani, Refka; Saidani, Taoufik; Horrigue, Layla; Atri, Mohamed

doi:10.1109/wccais.2014.6916602

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…JPEG2000 standard uses a wavelet-based method to provide better rate-distortion performance than the original JPEG [794]. The embedded wavelet coding algorithm know as EBCOT (Embedded Block Coding with Optimized Truncation of bit-stream), used for JPEG2000 standard, has been widely implemented in FPGAs for parallel optimization [795][796][797][798][799][800].…”

Section: Compression Standardsmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Section: Compression Standardsmentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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“…Several researchers have addressed their effort toward some of these algorithms in the past years [Chen et al 2012;Ghodhbani et al 2014]. In this article, we focus our attention to Chambolle [2004], which is a relevant algorithm belonging to this class and for which a highperformance parallel implementation has not yet been proposed, as we show in the analysis of the state-of-the-art approaches presented in Section 2.…”

Section: Introductionmentioning

confidence: 99%

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

Beretta

Rana

Akın

et al. 2016

ACM Trans. Embed. Comput. Syst.

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The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as graphics processing units (GPUs) or fieldprogrammable gate arrays (FPGAs), which are often employed to support the tasks of general-purpose processors (GPPs). One of the main advantages of these accelerators over their sequential counterparts (GPPs) is their ability to perform massive parallel computation. However, to exploit this competitive edge, it is necessary to extract the parallelism from the target algorithm to be executed, which generally is a very challenging task.This concept is demonstrated, for instance, by the poor performance achieved on relevant multimedia algorithms, such as Chambolle, which is a well-known algorithm employed for the optical flow estimation. The implementations of this algorithm that can be found in the state of the art are generally based on GPUs but barely improve the performance that can be obtained with a powerful GPP. In this article, we propose a novel approach to extract the parallelism from computation-intensive multimedia algorithms, which includes an analysis of their dependency schema and an assessment of their data reuse. We then perform a thorough analysis of the Chambolle algorithm, providing a formal proof of its inner data dependencies and locality properties. Then, we exploit the considerations drawn from this analysis by proposing an architectural template that takes advantage of the fine-grained parallelism of FPGA devices. Moreover, since the proposed template can be instantiated with different parameters, we also propose a design metric, the expansion rate, to help the designer in the estimation of the efficiency and performance of the different instances, making it possible to select the right one before the implementation phase. We finally show, by means of experimental results, how the proposed analysis and parallelization approach leads to the design of efficient and highperformance FPGA-based implementations that are orders of magnitude faster than the state-of-the-art ones.

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Analysis and implementation of parallel causal bit plane coding in JPEG2000 standard

Cited by 2 publications

References 7 publications

Field Programmable Gate Array Applications—A Scientometric Review

Field Programmable Gate Array Applications—A Scientometric Review

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

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