Analysis and Modeling of Vertical Current Conduction and Breakdown Mechanisms in Semi-Insulating GaN Grown on GaN: Role of Deep Levels

Stoklas, R.; Chvála, Aleš; Šichman, Peter; Hasenöhrl, S.; Hašc̆ı́k, Š.; Priesol, J.; Satka, A.; Kuzmı́k, J.

doi:10.1109/ted.2021.3065893

Cited by 5 publications

(7 citation statements)

References 30 publications

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“…[ 23 ] Alternative factors which may explain the difference include probability of higher radiation damage on the c ‐plane surface during (perpendicular) etching and ambiguity of the SI GaN thickness determination. [ 4 ] Suggested positive charge at the interface may correspond with elsewhere analyzed nonpolar GaN MOS structures showing negative shift of the flatband voltage. [ 21 ]…”

Section: Resultsmentioning

confidence: 68%

“…

Recently, we have suggested that the vertical transistor processing can be simplified by using a C-doped semi-insulating (SI) GaN as a channel layer. [3,4] Elsewhere, unspecified C-doping was introduced in the channel of the vertical normally off FET to compensate residual donors, still the n-type conduction of the GaN prevailed showing free-electron concentration (n) of %3 Â 10 15 cm À3 . [5] Consequently, the width of the channel depletion region (w) induced by the grounded gate was still insufficient to avoid necessity of the channel nanopatterning if normally off behavior was expected.

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confidence: 99%

“…[7] Nevertheless, earlier we have shown that by reaching C concentration between 1 Â 10 17 and 6 Â 10 18 cm À3 , GaN became highly insulating with a breakdown voltage between 45 and 350 V of a 1.3 μm thick layer. [3,4] We suggested, that while C-related acceptors %0.9 eV above the valence band are responsible for a compensation of residual donors, current blocking is controlled by an additional defect-related acceptor level %0.6 eV bellow the conduction band. This way, an avalanche breakdown could be reached for a sufficiently high C doping, [4] while channel opening could be provided by a positive gate bias along trench openings.…”

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confidence: 99%

“…[3,4] We suggested, that while C-related acceptors %0.9 eV above the valence band are responsible for a compensation of residual donors, current blocking is controlled by an additional defect-related acceptor level %0.6 eV bellow the conduction band. This way, an avalanche breakdown could be reached for a sufficiently high C doping, [4] while channel opening could be provided by a positive gate bias along trench openings. Consequently, if successfully implemented, this concept could provide a unipolar switching in normally off GaN transistors without a need of nano-patterning.…”

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confidence: 99%

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Vertical GaN Transistor with Semi‐Insulating Channel

Šichman

Stoklas

Hasenöhrl

et al. 2023

Physica Status Solidi (a)

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Herein, vertical GaN transistors with a semi‐insulating (SI) 1.3 μm thick channel layer and C doping of 1 × 1017 cm−3 are studied. Structures are grown using a metal–organic chemical vapor deposition on conductive GaN substrates. SI GaN is sandwiched between 2.5 μm thick n‐GaN drift layer (Si doping of ≈ 1 × 1017 cm−3) and a top n‐GaN contact layer. A circular mesa region with a diameter of 180 μm is patterned using a deep dry etching. The gate contact formed on the mesa sidewall is insulated from the vertical channel using a 20 nm thick Al2O3 grown by an atomic layer deposition. Despite a robust layout, transistors transfer characteristics indicate normally off behavior if extracted from the linearly scaled current–voltage characteristics and an open channel drain current of 30 mA at the gate bias of 4 V. Achieved on/off ratio is 107 at −2 V subthreshold gate bias when the full channel depletion is reached. And, 200 ns long gate pulse characteristics show only a marginal trapping even though no post‐metallization annealing is performed. By comparing experimental results with modeling, mobility of free electrons in the channel is found to be about 45 cm2 V−1 s−1.

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Section: Resultsmentioning

confidence: 68%

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confidence: 99%

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confidence: 99%

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confidence: 99%

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Vertical GaN Transistor with Semi‐Insulating Channel

Šichman

Stoklas

Hasenöhrl

et al. 2023

Physica Status Solidi (a)

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“…The stack was deposited from NH 3 and trimethylgallium (TMGa) in an H 2 reactor environment. The growth parameters of the thick buffer layer were optimized to achieve high electrical resistance by compensating native n-type defect levels that originate in nitride crystals from carbon doping due to the thermal decomposition of TMGa molecules in the reactor [18,19]. The thin top GaN layer was left undoped to secure a high crystalline quality and high charge carrier mobility.…”

Section: Methodsmentioning

confidence: 99%

In(Ga)N 3D Growth on GaN-Buffered On-Axis and Off-Axis (0001) Sapphire Substrates by MOCVD

et al. 2022

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In(Ga)N epitaxial layers were grown on on-axis and off-axis (0001) sapphire substrates with an about 1100 nm-thick GaN buffer layer stack using organometallic chemical vapor deposition at 600 °C. The In(Ga)N layers consisted of a thin (~10–25 nm) continuous layer of small conical pyramids in which large conical pyramids with an approximate height of 50–80 nm were randomly distributed. The large pyramids were grown above the edge-type dislocations which originated in the GaN buffer; the dislocations did not penetrate the large, isolated pyramids. The large pyramids were well crystallized and relaxed with a small quantity of defects, such as dislocations, preferentially located at the contact zones of adjacent pyramids. The low temperature (6.5 K) photoluminescence spectra showed one clear maximum at 853 meV with a full width at half maximum (FWHM) of 75 meV and 859 meV with a FWHM of 80 meV for the off-axis and on-axis samples, respectively.

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Comparative analysis of nonlinear behavioral models for GaN HEMTs based on machine learning techniques

Liu,

Cai

2023

Int J Numerical Modelling

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A variety of novel behavioral modeling techniques have been reported to accurately capture the nonlinear characteristics of GaN devices. For the purpose of describing GaN HEMT large‐signal behavior, machine learning‐based approaches have been proposed. There is, however, a lack of comparison and analysis of their performance with different machine learning techniques in these studies. An examination of machine learning‐based large‐signal modeling techniques is presented in this article. To develop large‐signal models of GaN HEMT, a range of commonly used modeling techniques such as artificial neural networks (ANN), random sample consistency (RANSAC), support vector regression (SVR), Gaussian process regression (GPR), decision trees (DTs), and genetic algorithm‐assisted ANN (GA‐ANN) are described and employed. Afterwards, integrated modeling techniques such as Bootstrap aggregation (BA), random forests (RF), AdaBoost, and gradient tree boosting (GTB) are reviewed and tested for their capabilities in developing GaN HEMT LSM. The hyperparameters of each built model are modified using the random search optimization (RSO) method, and five‐fold cross‐validation is used during validation. In order to identify optimal algorithms for nonlinear behavioral modeling of GaN devices, the model prediction results are comprehensively analyzed.

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Analysis and Modeling of Vertical Current Conduction and Breakdown Mechanisms in Semi-Insulating GaN Grown on GaN: Role of Deep Levels

Cited by 5 publications

References 30 publications

Vertical GaN Transistor with Semi‐Insulating Channel

Vertical GaN Transistor with Semi‐Insulating Channel

In(Ga)N 3D Growth on GaN-Buffered On-Axis and Off-Axis (0001) Sapphire Substrates by MOCVD

Comparative analysis of nonlinear behavioral models for GaN HEMTs based on machine learning techniques

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