Analysis and Optimization of Threshold Voltage Variability by Polysilicon Grain Size Simulation in 3D NAND Flash Memory

Yang, Tao; Xia, Zeyang; Shi, Dandan; Ouyang, Yingjie; Huo, Zongliang

doi:10.1109/jeds.2020.2970450

Cited by 16 publications

(7 citation statements)

References 16 publications

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“…To determine the cause, the PED is used to quantify the grain size of analyzed samples, and the LTA-m obtains a larger grain size than RTA. Then the grain size distribution was applied to the Sentaurus TCAD simulation based on [ 22 ], and the dopant activation rate of fitted Id-Vg curves was extracted. The simulation shown in Figure 3 shows that the boron activation rate of LTA-m is at least 23% higher than the RTA method.…”

Section: Resultsmentioning

confidence: 99%

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

et al. 2023

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The bit density is generally increased by stacking more layers in 3D NAND Flash. Lowering dopant activation of select transistors results from complex integrated processes. To improve channel dopant activation, the test structure of vertical channel transistors was used to investigate the influence of laser thermal annealing on dopant activation. The activation of channel doping by different thermal annealing methods was compared. The laser thermal annealing enhanced the channel activation rate by at least 23% more than limited temperature rapid thermal annealing. We then comprehensively explore the laser thermal annealing energy density on the influence of Poly-Si grain size and device performance. A clear correlation between grain size mean and grain size sigma, large grain size mean and sigma with large laser thermal annealing energy density. Large laser thermal annealing energy density leads to tightening threshold voltage and subthreshold swing distribution since Poly-Si grain size regrows for better grain size distribution with local grains optimization. As an enabler for next-generation technologies, laser thermal annealing will be highly applied in 3D NAND Flash for better device performance with stacking more layers, and opening new opportunities of novel 3D architectures in the semiconductor industry.

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Section: Resultsmentioning

confidence: 99%

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

et al. 2023

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“…The parameters of the simulation structure are based on the current technology products. Furthermore, the drift–diffusion model, Coulomb scattering mobility model, thermionic emission, Shockley–Read–Hall recombination, and band-to-band-tunneling (BTBT) model were introduced in the polysilicon channel, which was well-calibrated based on our previous works [ 18 ] and GIDL current experiments. The inset shows the detailed structure of the GIDL transistors.…”

Section: Simulationsmentioning

confidence: 99%

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

et al. 2023

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The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of Vdb_max and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash.

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“…Due to the intrinsic variation of V th distribution of the cells, the main challenge is to place the cell to the desired V th level with high precision. [109,110] Therefore, ensuring the V th gap is one of the most crucial issues in current NAND technology. This has been accomplished by the ISPP technique, [111,112] which proceeds as follows.…”

Section: Multilevel Cellsmentioning

confidence: 99%

Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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Analysis and Optimization of Threshold Voltage Variability by Polysilicon Grain Size Simulation in 3D NAND Flash Memory

Cited by 16 publications

References 16 publications

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

Activation Enhancement and Grain Size Improvement for Poly-Si Channel Vertical Transistor by Laser Thermal Annealing in 3D NAND Flash

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

Review of Semiconductor Flash Memory Devices for Material and Process Issues

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