Analysis and reduction of SRAM PUF Bit Error Rate

Shinohara, Hirofumi; Zheng, Baikun; Piao, Yanhao; Liu, Bo; Liu, Shiyu

doi:10.1109/vlsi-dat.2017.7939688

Cited by 13 publications

(1 citation statement)

References 5 publications

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“…A bit error rate (BER) of at least 10 −6 is assumed to be adequate for any realistic application [9]. Since the initial values of SRAM at start-up impose a higher BER (10% and more), techniques using error correction codes (ECCs) [7], pre-selection methods [10], or hardening [11] are used to reduce the BER of the PUF. The deployment of the first two techniques proceeds in two phases, enrollment and reconstruction.…”

Section: B Applicationsmentioning

confidence: 99%

Single-Chip Motes and SRAM PUF: Feasibility Study

Faour,

Korecic,

Vučinić

et al. 2024

2024 IEEE Workshop on Crystal-Free/-Less Radio and System-Based Research for IoT (CrystalFreeIoT)

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Physically unclonable functions (PUFs) are used as low-cost cryptographic primitives that extract key material from manufacturing variabilities of a device. All microcontrollers have on-chip SRAM; the power-up state of SRAM cells provides one way of obtaining a random output. However, not every SRAM can be used as a PUF. SRAM PUFs need to fulfill certain requirements: randomness, reliability, unpredictability and uniqueness. In this paper, we study whether the SRAM present on a novel class of devices, single-chip motes, satisfies these requirements. Single-chip motes are wireless sensor nodes that integrate computation, communication, power and sensing on a single chip. We analyze the SRAM characteristics on nine different single-chip motes to understand the potential of using these integrated SRAMs as PUF. Our experiments on 55 kB SRAM for each mote indicate that SRAM start-up values satisfy the requirements. Therefore, these embedded memories can be used for different PUF applications, including secret key extraction and true random number generation.

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