Analysis and Simulation of Mixed-Technology VLSI Systems

Martin, Dale E.; Radhakrishnan, R.; Rao, Dhananjai M.; Chetlur, Malolan; Subramani, Krishnan; Wilsey, Philip A.

doi:10.1006/jpdc.2001.1805

Cited by 11 publications

(5 citation statements)

References 48 publications

(56 reference statements)

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“…Several parallel simulators of electronic circuits have been developed recently, such as Xyce [4], TITAN [5], and SEAMS [6]. FineSim Spice from Magma Inc. is a commercial transistorlevel circuit simulator for mixed-signal SoCs that can run over distributed networks or multi-CPU workstations [7].…”

Section: Related Workmentioning

confidence: 99%

“…The amount of parallelism inherent to the circuit limits the partitioning success [6] and some of the algorithms give good results only on mutually independent subcircuits. However, in typical ICs, the elements are highly connected including strong feed-back signals, and partitioning generates many connections between the partitions causing significant inter-partition load and consequently longer simulation runtimes.…”

Section: Related Workmentioning

confidence: 99%

“…4). Such aggregation of communication messages in larger groups before sending them across the network minimizes communication overhead [6].…”

Section: Parallel Simulation Algorithm Implementationmentioning

confidence: 99%

See 2 more Smart Citations

Grid-Enabled Parallel Simulation Based on Parallel Equation Formulation

Andjelkovic¹,

Litovski²,

Zerbe³

2010

ETRI J

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Parallel simulation is an efficient way to cope with long runtimes and high computational requirements in simulations of modern complex integrated electronic circuits and systems. This paper presents an algorithm for parallel simulation based on parallelization in equation formulation and simultaneous calculation of matrix contributions for nonlinear analog elements. In addition, the paper describes the development of a grid interface for a parallel simulator that enables a designer to perform simulations on distant computer clusters. Performances of the developed parallel simulation algorithm are evaluated by simulation of a microelectromechanical system.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Grid-Enabled Parallel Simulation Based on Parallel Equation Formulation

Andjelkovic¹,

Litovski²,

Zerbe³

2010

ETRI J

View full text Add to dashboard Cite

show abstract

“…However, the computation of outputs takes some time at the cosimulator and new tokens remain pending for next simulation iteration. This latency by virtue of the nature of TDF dataflow takes care of time warp problems in simulations: rolling back [38], lazy re-evaluation [39], cancellation [40], runahead (e.g., Calaveras algorithm by Synopsys); and slower lock-step algorithm in selecting smallest step for forced synchronization. The execution order of each TDF block is preset and the graph is cyclically directed; the cosimulator follows the order determined by SystemC AMS static scheduler at elaboration [33].…”

Section: Synchronizationmentioning

confidence: 99%

On Mixed Abstraction, Languages, and Simulation Approach to Refinement with SystemC AMS

Zaidi¹,

Grimm²,

Haase³

2010

EURASIP Journal on Embedded Systems

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Executable specifications and simulations are cornerstone to system design flows. Complex-mixed-signal embedded systems can be specified with SystemC AMS which supports abstraction and extensible models of computation. The language contains semantics for module connections and synchronization required in analog and digital interaction. Through the synchronization layer, user defined models of computation, solvers and simulators can be unified in the SystemC AMS simulator for achieving low-level abstraction and model refinement. These improvements assist in amplifying model aspects and their contribution to the overall system behavior. This work presents cosimulating refined models with timed data flow paradigm of SystemC AMS. The methodology uses C-based interaction between simulators. An RTL model of data encryption standard is demonstrated as an example. The methodology is flexible and can be applied in early design decision tradeoff, architecture experimentation, and particularly for model refinement and critical behavior analysis.

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“…While some effort on distributed VHDL simulation had been made [8], [10], [11], this was not the case for Verilog. DVS [9] was the first environment for parallel Verilog simulation.…”

Section: Introductionmentioning

confidence: 98%

On the Scalability of Parallel Verilog Simulation

Meraji

Zhang

Tropper

2009

2009 International Conference on Parallel Processing

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As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this paper, we examine the performance of a parallel Verilog simulator on four large, real designs. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. We develop a parser for Verilog files enabling us to simulate in parallel all synthesizable Verilog circuits. We utilize four circuits as our test benches; the LEON Processor with 200k gates, the OpenSparc T2 processor with 400k gates and two Viterbi decoder circuits with 100k and 800k gates respectively. The simulator makes use of XTW and to our knowledge is the first Verilog simulator which can parse all synthesizable Verilog files. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800k gates. The simulators' performance was shown to be scalable.

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Analysis and Simulation of Mixed-Technology VLSI Systems

Cited by 11 publications

References 48 publications

Grid-Enabled Parallel Simulation Based on Parallel Equation Formulation

Grid-Enabled Parallel Simulation Based on Parallel Equation Formulation

On Mixed Abstraction, Languages, and Simulation Approach to Refinement with SystemC AMS

On the Scalability of Parallel Verilog Simulation

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