Analysis and simulation of MOSFET-based gate-voltage-independent capacitor

Li, Shuowei; Ojima, Naoki; Xu, Zule; Iizuka, Tetsuya

doi:10.35848/1347-4065/ac6406

Cited by 4 publications

References 27 publications

(22 reference statements)

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An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC

Li,

Yang,

Iizuka

2024

Circuits Syst Signal Process

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This paper proposes an 8-bit synthesizable SAR ADC with inverter-cell-based capacitive digital-to-analog converters (CDACs). An inverter-cell-based capacitor is proposed by connecting the supply and ground ports of the inverter cells together but leaving them floated to suppress the voltage dependence to be suitable for employment in an ADC with moderate resolution. Furthermore, an inverter-cell-based analog switch is proposed to be employed in S/H and CDAC to achieve a fully standard-cell-based design without any custom-designed cells. The prototype is fabricated in a 65 nm standard CMOS process occupying 0.19 mm2. With a Nyquist input, the SFDR and SNDR reach 53.6 dB and 46.2 dB at 2.92 MS/s respectively without calibration. The power consumption is 425 $${\mu }$$ μ W from a 1.2 V supply, which leads to the Walden FoM of 0.86 pJ/conv.-step.

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An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC

Li,

Yang,

Iizuka

2024

Circuits Syst Signal Process

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Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Sanjay,

Kumar,

Vohra

2024

Silicon

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Ultrathin nanocapacitor assembled via atomic layer deposition

Lopez Medina,

Mejía-Salazar,

Carvalho

et al. 2024

Nanotechnology

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We fabricated ultrathin metal - oxide - semiconductor (MOS) nanocapacitors using atomic layer deposition. The capacitors consist of a bilayer of Al2O3 and Y2O3 with a total thickness of ~10 nm, deposited on silicon substrate. The presence of the two materials, each slab being ~5 nm thick and uniform over a large area, was confirmed with Transmission Electron Microscopy and X-ray photoelectron spectroscopy (XPS). The capacitance in accumulation varied from 1.6 nF (at 1MHz) to ~2.8 nF (at 10 kHz), which is one to two orders of magnitude higher than other nanocapacitors. This high capacitance is attributed to the synergy between the dielectric properties of ultrathin Al2O3 and Y2O3 layers. The electrical properties of the nanocapacitor are stable within a wide range of temperatures, from 25 °C to 150 °C, as indicated by capacitance-voltage (C - V). Since the thickness-to-area ratio is negligible, the nanocapacitor could be simulated as a single parallel plate capacitor in COMSOL Multiphysics, with good agreement between experimental and simulation data. As a proof-of-concept we simulated a MOSFET device with the nanocapacitor gate dielectric, whose drain current is sufficiently high for micro and nanoelectronics integrated circuits, including for applications in sensing.

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Analysis and simulation of MOSFET-based gate-voltage-independent capacitor

Cited by 4 publications

References 27 publications

An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC

An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC

Quantization Effect in N-Channel Inversion Mode Si, In0.53Ga0.47As and Ge Based Double Gate MOSFET Using Quasi-Static Capacitance–Voltage Characteristics for Upcoming Sub 10 nm Technology Node

Ultrathin nanocapacitor assembled via atomic layer deposition

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