Analysis, Design, and Performance Evaluation of a Dynamically Slew Enhanced Adaptively Biased Capacitor-Less Low Dropout Regulator

Abstract

Dynamically slew enhanced adaptive bias (DSE-AB) scheme has been recently introduced for an externally compensated (with-capacitor) regulator for achieving a very fast transient response. The combined effects of enhanced slew rate and expanded loop bandwidth using the DSE-AB scheme produce a very low undershoot and overshoot. When this scheme is directly applied to an internally compensated, capacitor-less low dropout regulator (CL-LDR) topology, besides the slew enhancement, the instantaneous dynamic current may reduce the damping factor momentarily and produce more ringing in the load transient response. This paper first analyzes the generation of momentary low damping factor in the CL-LDR that uses the DSE-AB scheme. A current limited DSE-AB scheme is also proposed to increase the momentary damping factor for minimizing the ringing in the settling behavior. To validate the proposed scheme, the CL-LDR is implemented in a 0.18 µm CMOS technology and the regulator's performance is evaluated in different dynamic conditions. Experimental result shows an undershoot of 45 mV during 0-100 mA load step and an overshoot of 25 mV during the other edge.Index Terms-Low dropout regulator, capacitor-less regulator, damping factor, main feedback loop, adaptive bias loop.

An External Capacitor-Less Low-Dropout Voltage Regulator Using a Transconductance Amplifier

“…Academic research works [6] can achieve low dropout voltage, but [6] does not provide the data of V OUT when I OUT is smaller than 30 mA. Also, all of these academic research works including [6], [15] and [7] do not consider the wide temperature operation and package. Finally, Figure of Merit (FOM) are compared by using [6]:…”

“…There are many proposed state-of-the-art LDO topologies , which feature capless [7], [8], fast transient [9]- [11], and so on. However, most of the researches do not consider ultra-large output currents, the package and a broad range of temperature operation.…”

High voltage low quiescent current LDO with self-regulation impedance buffer

“…With the improving demands of the green power IC (integrated circuit), the LDO (low-dropout regulator) with its low power consumption and stable output voltage gets a lot of applications [1][2][3]. During the design process, low dropout voltage, low consumption, adequate output current and the fast-transient response are four main issues which should be focused [4,5].…”

A fast transient response and high current efficiency output-capacitorless low dropout regulator for low-power SoC applications

“…Because of their relatively small chip area and simple design, output capacitor-less low-dropout regulators (LDOs) have been widely used in RF, analog, and digital circuits and SoC systems. [1][2][3][4][5][6][7][8][9][10][11][12][13] However, compensating for the changes in output poles is usually difficult primarily because of the insufficient stability at high load impedances.…”

“…In addition to improving the charge and discharge of the transmission transistor for enhancing the transient response, studies have proposed adaptive biasing architectures that vary with load current. [2][3][4] The nested miller compensation technique 4) actives when the transient response occurs the intensity of I v would increase the bandwidth with the increase of the adaptively biased, and quickly ameliorate the voltage undershoot. Conversely, when the output load current is switched from heavy to light, the system rapidly detects the voltage variation from the originally improved high loop bandwidth system and rapidly reduces the bandwidth for reducing the voltage overshoot.…”