Accelerated tests for Single Event Effect (SEE) that irradiate the target with far higher fluence beam are typically applied to investigate the device sensitivity to atmospheric neutron. Considering the neutrality and strong penetrability of neutron, devices are frequently placed in parallel to save time. For nanoscale devices, however, the results may be significantly influenced. The possibility of applying multiple-board parallel testing in accelerated experiments of atmospheric-neutron-induced soft errors was investigated using a 22-nm Static Random-Access Memory (SRAM) Field Programmable Gate Array (FPGA). To simplify the analysis, several empty Printed Circuit Boards (PCBs) were employed as the upstream boards. Both Block Random-Access Memory (BRAM) and Configuration Random-Access Memory (CRAM) were tested under the neutron beam provided by Atmospheric Neutron Irradiation Spectrometer (ANIS), showing similar results. For high-energy neutrons, device sensitivity decreases as the number of upstream PCBs increases, although the influence seems weak. The drop in cross sections from no-PCB to 20-PCBs is less than 30% for both modules. For thermal neutron testing, however, its sensitivity was greatly suppressed by PCBs. Epoxy resin contained in PCBs is considered to be the key factors for these phenomena due to its high content of hydrogen. Also, neutron can be scattered by copper to lose energy or even be absorbed by it. As a result, the actual fluence of the neutron reaching the device was reduced. Therefore, parallel testing may not be suitable if thermal neutrons need to be considered, but it is practicable for high-energy neutron testing with proper correction algorithms applied. SRAM FPGA, SOFT ERROR, ATMOSPHERIC-NEUTRON, PARALLEL TEST