“…Nevertheless, there is no uniform standard for investigating the SC capability of SiC devices so far, as the JEDEC Solid State Technology Association provides testing standards for Si devices. Considering complex failure modes (gate failure and thermal runaway) and the delayed failure phenomenon, which is related to VGS, VDS, case temperature, and SC pulse wide [8], [47], [50], [51], [52], the method with continuously applying SC stress until the test circuit is cut off by the series protection will ignore the delayed failure phenomenon and lead to an overestimation of ESC [39], [49]. According to the reported literature, the common method uses the test sequence in Fig.…”