Analysis of data dependence of leakage current in CMOS cryptographic hardware

Giorgetti, Jacopo; Scotti, Giuseppe; Simonetti, Andrea; Trifiletti, Alessandro

doi:10.1145/1228784.1228808

Cited by 30 publications

(25 citation statements)

References 10 publications

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“…This illustrates the dep current on input patterns. The same observed in PMOS transisto exploited to wage leakage-bas cryptographic systems [3,4,19]. T of LPA will be explained in the nex …”

Section: ) Leakage Power Dependency On Input Pmentioning

confidence: 64%

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Power balanced circuits for leakage-power-attacks resilient design

Halak

Murphy

Yakovlev

2015

2015 Science and Information Conference (SAI)

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The continuous rise of static power consumption in modern CMOS technologies has led to the creation of a novel class of security attacks on cryptographic systems. The latter exploits the correlation between leakage current and the input patterns to infer the secret key; it is called leakage power analysis (LPA). The use power-balanced (m-of-n) logic is a promising solution that provides an answer to this problem, such circuits are designed to consume constant amount of power regardless of data being processed. This work evaluates the security of cryptographic circuits designed with this technology against the newly developed LPA. Two forms of LPA are investigated, one is based on differential power analysis (LDPA) and the other based on Hamming weight analysis (LHPA). Simulations performed at 90nm CMOS technology reveal that (m-of-n) circuits are totally resilient to LHPA and have a higher security level against LDPA than standard logic circuits.

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Section: ) Leakage Power Dependency On Input Pmentioning

confidence: 64%

“…LHPA exploits the correlation between the hamming weight of the input patterns of a circuits and its leakage power to reveal its secret key [2,3,19]. It is easier to wage than LDPA as it needs a fewer number of leakage power measurements.…”

Section: ) Leakage-base Hamming-weight Power Attack (Lhpa)mentioning

confidence: 99%

Power balanced circuits for leakage-power-attacks resilient design

Halak

Murphy

Yakovlev

2015

2015 Science and Information Conference (SAI)

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“…This increasing trend has drawn attention to leakage power which will likely offer a new power related side channel threat. By far the only resources showing results of a successful DPA attack using leakage power consumption are [6] [7]. Further observation can be made by considering the results in [6] and [7].…”

Section: Leakage Power: a New Side Channelmentioning

confidence: 99%

“…The role of leakage power consumption as a side channel has not been addressed until recently in [7] [8]. A conclusive outcome in [7] presented the deterministic result of attack based on minimum leakage current. Feasibility of exploiting the leakage power consumption in side channel attacks was proven in [8].…”

Section: Introductionmentioning

confidence: 99%

Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)

Zadeh

Gebotys

2009

2009 10th International Symposium on Quality of Electronic Design

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This paper investigates the potential security threat to nanoscale Cryptosystem-on-Chip (CoC) posed by the leakage power consumption. The increasing trend of leakage power is shown to be highly correlated with increasing side channel vulnerability. The effect of high threshold voltage (V th ) transistor assignment on improving side channel resistance is analyzed. This investigation shows growth of the leakage mechanisms such as directtunneling and Band-to-Band Tunneling (BTBT) currents may reduce the effectiveness of the high V th transistor assignment technique; however, this technique can still be used in developing side channel resistant cryptosystem. This research is crucial for security sensitive architecture and the results are obtained leading to side channel aware leakage management in design and implementation of CoC in submicron technology.

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“…A. Moradi recently demonstrated successful power-analysis attacks exploiting the static leakage of FPGAs in [28]. Other works also characterized and exploited static leakages of CMOS devices, for example, in [18,26].…”

Section: Temperature Analysismentioning

confidence: 99%

The Temperature Side Channel and Heating Fault Attacks

Hutter

Schmidt²

2014

Lecture Notes in Computer Science

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Abstract. In this paper, we present practical results of data leakages of CMOS devices via the temperature side channel-a side channel that has been widely cited in literature but not well characterized yet. We investigate the leakage of processed data by passively measuring the dissipated heat of the devices. The temperature leakage is thereby linearly correlated with the power leakage model but is limited by the physical properties of thermal conductivity and capacitance. We further present heating faults by operating the devices beyond their specified temperature ratings. The efficiency of this kind of attack is shown by a practical attack on an RSA implementation. Finally, we introduce data remanence attacks on AVR microcontrollers that exploit the Negative Bias Temperature Instability (NBTI) property of internal SRAM cells. We show how to recover parts of the internal memory and present first results on an ATmega162. The work encourages the awareness of temperature-based attacks that are known for years now but not well described in literature. It also serves as a starting point for further research investigations.

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Analysis of data dependence of leakage current in CMOS cryptographic hardware

Cited by 30 publications

References 10 publications

Power balanced circuits for leakage-power-attacks resilient design

Power balanced circuits for leakage-power-attacks resilient design

Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)

The Temperature Side Channel and Heating Fault Attacks

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